T89C51RD2-3CWC-M datasheet(23/86 Pages) ATMEL

23 / 86 page

Rev. F - 15 February, 2001

T89C51RD2

Figure 7. PCA Timer/Counter

Table 7. CMOD: PCA Counter Mode Register

The CMOD SFR includes three additional bits associated with the PCA (See Figure 7 and Table 7).

• The CIDL bit which allows the PCA to stop during idle mode.

• The WDTE bit which enables or disables the watchdog function on module 4.

CMOD

Address 0D9H

CIDL

WDTE

CPS1

CPS0

ECF

Reset value

Symbol

Function

CIDL

Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during

idle Mode. CIDL = 1 programs it to be gated off during idle.

WDTE

Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4.

WDTE = 1 enables it.

Not implemented, reserved for future use.a

User software should not write 1s to reserved bits. These bits may be used in future 8051 family

products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its

active value will be 1. The value read from a reserved bit is indeterminate.

CPS1

PCA Count Pulse Select bit 1.

CPS0

PCA Count Pulse Select bit 0.

CPS1

CPS0

Selected PCA input.b

fosc = oscillator frequency

Internal clock fosc/12 ( Or fosc/6 in X2 Mode).

Internal clock fosc/4 ( Or fosc/2 in X2 Mode).

Timer 0 Overflow

External clock at ECI/P1.2 pin (max rate = fosc/8)

ECF

PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an

interrupt. ECF = 0 disables that function of CF.

CIDL

CPS1

CPS0

ECF

16 bit up/down counter

To PCA

modules

Fosc /12

Fosc / 4

T0 OVF

P1.2

Idle

CMOD

0xD9

WDTE

CCON

0xD8

CCF4

CCF3

CCF2

CCF1

CCF0

overﬂow

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