©2000 California Micro Devices Corp. All rights reserved.

10/18/2000

215 Topaz Street, Milpitas, California 95035



Tel: (408) 263-3214

Fax: (408) 263-7846

www.calmicro.com

6

CMPWR025

CALIFORNIA MICRO DEVICES

TYPICAL TRANSIENT CHARACTERISTICS

The circuit schematic below shows the transient charac-

terization test setup. It includes the power supply source

impedances R

supplies’ output impedances and interconnection

parasitics to the V

up, the series resistances on V

tively R

otherwise. A load resistance R

load current of about 450mA at 5V.

The hysteresis level is increased by connecting pin 8 to

ground, which will improve the transient performance in

noisy environments. In the transient analysis, the rise

time and fall time of V

range, providing a worst case situation.

Important note: Power supply source impedance must

be as low as possible to avoid chatter during power

transition. When operating in a high load and long rise

time power-up condition, we recommend not exceeding

a value of 0.15

Ω on both source resistances.

V

I(R

S

+ R

Where: V

Rs = The Power Supply Output Impedance

R

For a rated load of 500mA, Rs + R

Input and Output Capacitors

Filtering is typically unnecessary on the inputs, however

power supply source impedance and parasitic resistance

or inductance on the interconnections may result in

chattering during the supply changeover. When an input

is deselected and the input current drops to zero, the

voltage at the input terminals will rise. If this voltage rise

exceeds the hysteresis (75mV typical), the switch may

chatter.

There are four ways to eliminate this chatter:

• Connect pin 8 to GND to select 150mV

hysteresis,

• Position the device as close as possible to the

power supply connectors,

• Use low-impedance PCB traces, or

• Include low-ESR input bypass capacitors at the

V

greater are recommended.

V

output is glitch-free during dynamic switching of the

inputs, it is recommended that an external capacitor of

10µF or greater is included. This will restrict any tran-

sient output disturbances to less than 300mV at 500mA

loading during dynamic switching of the inputs.

The test set-up used in Figures 4 and 5 is described on

page 5. The set-up for Figure 6 has larger series

resistances on V

V

Figure 4 shows

the primary supply V

to 5V transition. The secondary supply V

DC. The channel 1 switch is turned on when V

within about 70mV of V

due to power supply source resistance R

glitch appears on V

off, due to power supply inductance. This has no effect

on the output voltage.

C6

10µF

C5

0.1µF

Load

11

Ω

+

5V

TR = 20ms

TF= 20ms

GND

HYS

GND

CMPWR025

+

–

5V

C3

0.1µF

C4

10µF

+

GND

C1

0.1µF

C2

10µF

+

Transient Characterization Test Set-up