AD7989-5BCPZ-R2 datasheet(20/24 Pages) ETC2

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AD7989-1/AD7989-5

Data Sheet

Rev. 0 | Page 20 of 24

APPLICATIONS INFORMATION

INTERFACING TO BLACKFIN® DSP

The AD7989-1/AD7989-5 can easily connect to a DSP SPI or

SPORT. The SPI configuration is straightforward using the

standard SPI interface, as shown in Figure 37.

Figure 37. Typical Connection to Blackfin SPI Interface

Similarly, the SPORT interface can be used to interface to this

ADC. The SPORT interface has some benefits in that it can use

direct memory access (DMA) and provides a lower jitter CNV

signal generated from a hardware counter.

Some glue logic may be required between SPORT and the

AD7989-1/AD7989-5 interface. The evaluation board for the

AD7989-1/AD7989-5 interfaces directly to the SPORT of the

Blackfin-based (ADSP-BF527) SDP board. The configuration

used for the SPORT interface requires the addition of some glue

logic as shown in Figure 38. The SCK input to the ADC was

gated off when CNV was high to keep the SCK line static while

converting the data, thereby ensuring the best integrity of the

result. This approach uses an AND gate and a NOT gate for the

SCK path. The other logic gates used on the RSCLK and RFS

paths are for delay matching purposes and may not be

necessary when path lengths are short.

This is one approach to using the SPORT interface for this

ADC; there may be other solutions similar to this approach.

Figure 38. Evaluation Board Connection to Blackfin Sport Interface

LAYOUT

Design the printed circuit board that houses the AD7989-1/

AD7989-5 so that the analog and digital sections are separated

and confined to certain areas of the board. The pinout of the

AD7989-1/AD7989-5, with its analog signals on the left side

and its digital signals on the right side, eases this task.

Avoid running digital lines under the device because these

couple noise onto the die, unless a ground plane under the

AD7989-1/AD7989-5 is used as a shield. Do not run fast

switching signals, such as CNV or clocks, near analog signal

paths. Avoid crossover of digital and analog signals.

Using at least one ground plane is recommended. It can be

common or split between the digital and analog sections. In the

latter case, join the planes underneath the AD7989-1/AD7989-5

devices.

The AD7989-1/AD7989-5 voltage reference input, REF, has a

dynamic input impedance. Decouple REF with minimal

parasitic inductances by placing the reference decoupling

ceramic capacitor close to, but ideally right up against, the REF

and GND pins and connecting them with wide, low impedance

traces.

Finally, decouple the power supplies of the AD7989-1/AD7989-5,

VDD and VIO, with ceramic capacitors, typically 100 nF, placed

close to the AD7989-1/AD7989-5 and connected using short,

wide traces to provide low impedance paths and to reduce the

effect of glitches on the power supply lines.

An example of a layout following these rules is shown in

Figure 39 and Figure 40.

AD7989-1/

AD7989-5

SCK

SDO

CNV

SPI_CLK

SPI_MISO

SPI_MOSI

DSP

SCK

SDO

CNV

TSCLK

TFS

RFS

RSCLK

VDRIVE

AD7989-1/

AD7989-5

BLACKFIN

DSP

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