| 数据搜索系统,热门电子元器件搜索 |
|
CS4297 数据表(PDF) 13 Page - Cirrus Logic |
|
|
|||||||||||||||||||||||||||||
CS4297 数据表(HTML) 13 Page - Cirrus Logic |
|
13 / 46 page ![]() DS242F5 13 CS4297 CrystalClear™ SoundFusion™ Audio Codec ’97 volume level. All analog volume controls, except PC_BEEP, implement controlled volume steps at nominally 1.5 dB per step. PC_BEEP uses 3 dB steps. The analog inputs allow a mixing range of +12 dB of signal gain to -34.5 dB of signal attenu- ation. The analog output volume controls allow from 0 dB to -94.5 dB of attenuation. The PC_BEEP input volume control allows from 0 dB to -45 dB of attenuation. AC’97 IMPLEMENTATION The CS4297 implements an AC’97 compliant de- sign as defined in the Intel Audio Codec 97 Speci- fication Version 1.03. Due to certain design trade- offs and implementation decisions, the CS4297 dif- fers from the AC’97 Specification in a a few minor ways. The following list captures the specification deviations and the implementation decisions made to resolve ambiguities. 1. The rising edge of RESET# must occur at least 1.5 ms after the digital power supply DVdd reaches 90% of maximum value. 2. The digital input voltage threshold levels are specified as percentages of the Vdd digital power supply and are TTL level compatible. Min Vih = 0.4 x Vdd, Max Vil = 0.16 x Vdd. 3. The delay between setting the PR4 bit to power- ing down the AC-Link interface is implemented as 16.24 µs. Figure 1. Mixer Diagram |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |