CS4297 datasheet(39/46 Pages) CIRRUS

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DS242F5

CS4297

CrystalClear™ SoundFusion™ Audio Codec ’97

PIN DESCRIPTIONS

Digital I/O Pins

RESET# - AC’97 Chip Reset, Input

This active low signal is the asynchronous Cold Reset input to the CS4297. The CS4297 must

be reset before it can enter normal operating mode.

SYNC - AC-link Serial Port Sync pulse, Input

This signal is the serial port timing signal for the AC-link of the CS4297. Its period is the

reciprocal of the sample rate of the CS4297, 48 kHz. This signal is generated by the AC’97

Controller and is synchronous to BIT_CLK. SYNC is also an asynchronous input when the

CS4297 is in a Warm Reset state. A series terminating resistor of 47

Ω should be connected on

this signal close to the device driving the signal.

BIT_CLK - AC-link Serial Port Master Clock, Output

This output signal controls the master clock timing for the AC-link. It is a 12.288 MHz clock

signal which is divided down by two from the XTL_IN input clock. A series terminating

resistor of 47

Ω should be connected on this signal close to the CS4297.

LINE_OUT_L

AFLT1

REFFLT

LINE_OUT_R

AFLT2

Vrefout

AVss1

AVdd1

13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37

BIT_CLK

XTL_IN

DVss1

SDATA_IN

SYNC

DVdd1

XTL_OUT

SDATA_OUT

DVdd2

RESET#

PC_BEEP

DVss2

CS4297 数据表(PDF) 39 Page - Cirrus Logic

CS4297 数据表(HTML) 39 Page - Cirrus Logic

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