CS49400 datasheet(91/100 Pages) CIRRUS

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This should be tied low for normal operation. INPUT

MCLK — Audio Master Clock

Bidirectional master audio clock. As an output, MCLK provides a low jitter oversampling clock.

MCLK supports all standard oversampling frequencies. BIDIRECTIONAL - Default: INPUT

SCLK0 — Audio Output Bit Clock

Bidirectional digital-audio output bit clock for AUDATA0, AUDATA1, AUDATA2, and AUDATA3.

As an output, SCLK0 can provide 32 Fs, 64 Fs, 128 Fs, 256 Fs, or 512 Fs frequencies and is

synchronous to MCLK. As an input, SCLK0 is independent of MCLK.

BIDIRECTIONAL - Default: INPUT

SCLK1 — Audio Output Bit Clock

Bidirectional digital-audio output bit clock for AUDATA4, AUDATA5, AUDATA6, and AUDATA7.

As an output, SCLK1 can provide 32 Fs, 64 Fs, 128 Fs, 256 Fs, or 512 Fs frequencies and is

synchronous to MCLK. As an input, SCLK1 is independent of MCLK.

BIDIRECTIONAL - Default: INPUT

LRCLK0 — Audio Output Sample Rate Clock

Bidirectional digital-audio output frame clock for AUDATA0, AUDATA1, AUDATA2, and

AUDATA3. As an output, LRCLK0 can provide all standard output sample rates up to 192 kHz

and is synchronous to MCLK. As an input, LRCLK0 is independent of MCLK.

BIDIRECTIONAL - Default: INPUT

LRCLK1 — Audio Output Sample Rate Clock

Bidirectional digital-audio output frame clock for AUDATA4, AUDATA5, AUDATA6, and

AUDATA7. As an output, LRCLK1 can provide all standard output sample rates up to 192 kHz

and is synchronous to MCLK. As an input, LRCLK1 is independent of MCLK.

BIDIRECTIONAL - Default: INPUT

AUDATA0 — Digital Audio Output 0

PCM digital-audio data output. OUTPUT

AUDATA1 — Digital Audio Output 1

PCM digital-audio data output. OUTPUT

AUDATA2 — Digital Audio Output 2

PCM digital-audio data output. OUTPUT

AUDATA3, XMT958A — Digital Audio Output 3, S/PDIF Transmitter

CS49400 数据表(PDF) 91 Page - Cirrus Logic