CS49400 datasheet(41/100 Pages) CIRRUS

41 / 100 page

5. CLOCKING

The CS49400 clock manager incorporates a

programmable phase locked loop (PLL) clock

synthesizer. The PLL takes an input reference

clock and produces all the clocks required to run

the DSP and peripherals.

In A/V Receiver designs, the CLKIN pin is

typically connected to a 12.288MHz oscillator.

The clock manager is controlled by the DSPAB

application software. The software user’s guide for

the application code being used should be

referenced for which CLKIN input frequency is

supported.

6. CONTROL

Control of the CS49400 can be accomplished

through one of three methods. The CS49400

supports SPI serial communication and Motorola®

and Intel® byte-wide parallel communication.

Both DSPAB and DSPC have their own control

ports. Only one of the three communication modes

can be selected for control. Both DSPAB and

DSPC use the same communication mode.

However, please note that the 100-pin package

only supports SPI serial communication. The states

of the FHS[2:0] for DSPAB and UHS[2:0] for

DSPC, sampled at the rising edge of RESET,

determine the communication interface (Table 2.)

Whichever host communication mode is used, host

control of the CS49400 is handled through the

application

software

running

the

DSP.

Configuration and control of the CS49400 decoder

and its peripherals are indirectly executed through

a messaging protocol supported by the downloaded

application code. In other words, successful

communication can only be accomplished by

following the low level hardware communication

format and high level messaging protocol. The

specifications of the messaging protocol can be

found in any of the software user’s guides, such as

AN208 and AN209.

The system designer only needs to read the

subsection describing the communication mode

being used. Please note that the communication

protocol might be slightly different for DSPAB and

DSPC.

The

following

sections

will

explain

each

communication mode in more detail. Flow

diagrams will illustrate read and write cycles.

The timing diagrams shown demonstrate relative

edge positions of signal transitions for read and

write operations.

6.1 Serial Communication

6.1.1 SPI Communication for DSPAB

SPI communication with DSPAB is accomplished

with five communication lines: chip select, serial

control clock, serial data in, serial data out, and an

interrupt request line that signals DSPAB has data

to transmit to the host. Table 4 lists the mnemonic,

144-Pin Package

FHS2

(Pin 7)

FHS1

(Pin 13

)

FHS0

(Pin 12)

Host Interface Mode

Serial SPI

8-bit Intel®

8-bit Motorola®

100-Pin Package

FHS2

(Pin 6)

FHS1

(Pin 10

)

FHS0

(Pin 9)

Host Interface Mode

Serial SPI

Table2.Host Modes forDSPAB

144-Pin Package

UHS2

(Pin 143)

UHS1

(Pin 2)

UHS0

(Pin 1)

Host Interface Mode

Serial SPI

8-bit Intel®

8-bit Motorola®

100-Pin Package

UHS2

(Pin 99)

UHS1

(Pin 2)

UHS0

(Pin 1)

Host Interface Mode

Serial SPI

Table 3. Host Modes for DSPC

CS49400 数据表(PDF) 41 Page - Cirrus Logic

CS49400 数据表(HTML) 41 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

数据表下载

链接网址

CS49400 数据表(PDF) 41 Page - Cirrus Logic

CS49400 数据表(HTML) 41 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

数据表 下载

链接网址

数据表下载