IO20PDB0V0 datasheet(27/197 Pages) MICROSEMI

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SmartFusion Customizable System-on-Chip (cSoC)

Re vi s i on 12

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Standby Mode

PDYN = PRC-OSC + PLPXTAL-OSC

Time Keeping Mode

PDYN = PLPXTAL-OSC

Global Clock Dynamic Contribution—PCLOCK

SoC Mode

PCLOCK = (PAC1 + NSPINE * PAC2 + NROW * PAC3 + NS-CELL * PAC4) * FCLK

NSPINE is the number of global spines used in the user design—guidelines are provided in the

"Device Architecture" chapter of the SmartFusion FPGA Fabric User's Guide.

NROW is the number of VersaTile rows used in the design—guidelines are provided in the "Device

Architecture" chapter of the SmartFusion FPGA Fabric User's Guide.

FCLK is the global clock signal frequency.

NS-CELL is the number of VersaTiles used as sequential modules in the design.

Standby Mode and Time Keeping Mode

PCLOCK = 0 W

Sequential Cells Dynamic Contribution—PS-CELL

SoC Mode

PS-CELL = NS-CELL * (PAC5 + (

α1 / 2) * PAC6) * FCLK

NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile

sequential cell is used, it should be accounted for as 1.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-17 on page 2-18.

FCLK is the global clock signal frequency.

Standby Mode and Time Keeping Mode

PS-CELL = 0 W

Combinatorial Cells Dynamic Contribution—PC-CELL

SoC Mode

PC-CELL = NC-CELL* (

α1 / 2) * PAC7 * FCLK

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-17 on page 2-18.

FCLK is the global clock signal frequency.

Standby Mode and Time Keeping Mode

PC-CELL = 0 W

Routing Net Dynamic Contribution—PNET

SoC Mode

PNET = (NS-CELL + NC-CELL) * (

α1 / 2) * PAC8 * FCLK

NS-CELL is the number VersaTiles used as sequential modules in the design.

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-17 on page 2-18.

FCLK is the frequency of the clock driving the logic including these nets.

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