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IO13PDB0V0 数据表(PDF) 36 Page - Microsemi Corporation |
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IO13PDB0V0 数据表(HTML) 36 Page - Microsemi Corporation |
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36 / 197 page ![]() SmartFusion DC and Switching Characteristics 2- 24 R e v i sio n 1 2 Summary of I/O Timing Characteristics – Default I/O Software Settings Table 2-21 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial Conditions in all I/O Bank Types DC I/O Standards Commercial IIL IIH µA µA 3.3 V LVTTL / 3.3 V LVCMOS 15 15 2.5 V LVCMOS 15 15 1.8 V LVCMOS 15 15 1.5 V LVCMOS 15 15 3.3 V PCI 15 15 3.3 V PCI-X 15 15 Table 2-22 • Summary of AC Measuring Points Applicable to All I/O Bank Types Standard Measuring Trip Point (Vtrip) 3.3 V LVTTL / 3.3 V LVCMOS 1.4 V 2.5 V LVCMOS 1.2 V 1.8 V LVCMOS 0.90 V 1.5 V LVCMOS 0.75 V 3.3 V PCI 0.285 * VCCxxxxIOBx (RR) 0.615 * VCCxxxxIOBx (FF) 3.3 V PCI-X 0.285 * VCCxxxxIOBx (RR) 0.615 * VCCxxxxIOBx (FF) LVDS Cross point LVPECL Cross point Table 2-23 • I/O AC Parameter Definitions Parameter Parameter Definition tDP Data to pad delay through the output buffer tPY Pad to data delay through the input buffer tDOUT Data to output buffer delay through the I/O interface tEOUT Enable to output buffer tristate control delay through the I/O interface tDIN Input buffer to data delay through the I/O interface tHZ Enable to pad delay through the output buffer—High to Z tZH Enable to pad delay through the output buffer—Z to High tLZ Enable to pad delay through the output buffer—Low to Z tZL Enable to pad delay through the output buffer—Z to Low tZHS Enable to pad delay through the output buffer with delayed enable—Z to High tZLS Enable to pad delay through the output buffer with delayed enable—Z to Low |
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