ACT412

Rev 1, 30-Oct-13

- 10 -

www.active-semi.com

Copyright © 2013 Active-Semi, Inc.

Active-Semi Proprietary―For Authorized Recipients and Customers

ActivePSR

TYPICAL APPLICATION CONT’D

Design Example

The design example below gives the procedure for

a DCM fly back converter using an ACT412. Refer

to Application Circuit Figure 2, the design for an

adapter application starts with the following

specification:

The operation for the circuit shown in Figure 1 is as

follows: the rectifier bridge D1-D4 and the capacitor

C1/C2 convert the AC line voltage to DC. This

voltage supplies the primary winding of the

transformer T1 and the startup resistor R7/R8 to

VDD pin of ACT412 and C4. The primary power

current path is formed by the transformer’s primary

winding, the mosfet, and the current sense resistor

R9. The resistors R3, R2, diode D5 and capacitor

C3 create a snubber clamping network that protects

Q1 from voltage spike from the transformer primary

winding

leakage

inductance.

The

network

consisting of capacitor C4, diode D6 and resistor

R4 provides a VDD supply voltage for ACT412 from

the auxiliary winding of the transformer. The resistor

R4 is optional, which filters out spikes and noise to

makes VDD more stable. C4 is the decoupling

capacitor of the supply voltage and energy storage

component for startup. During power startup, the

current charges C4 through startup resistor R7/R8

from the rectified high voltage. The diode D8 and

the capacitor C5/C6 rectify filter the output voltage.

The resistor divider consists of R5 and R6

programs the output voltage.

Since a bridge rectifier and bulk input capacitors are

used, the resulting minimum and maximum DC

input voltages can be calculated:

2х6.8µF electrolytic capacitors.

The full load system duty cycle is set to be 40% at

low line voltage 85VAC and the circuit efficiency is

estimated to be 75%. Then the average input

current at full load is:

The input primary peak current at full load:

The primary inductance of the transformer:

The primary turns on time at full load:

The ringing periods from primary inductance with

mosfet Drain-Source capacitor:

Design only an half ringing cycle at maximum load

in minimum low line, so secondly reset time:

Base on conservation of energy and transformer

transform identity, the primary to secondary turns

V

90

F

8

.

6

2

75

.

0

)

ms

5

.

3

47

2

1

(

5

2

85

2

C

)

t

f

2

1

(

P

2

V

2

V

2

IN

C

L

OUT

2

MIN

_

INAC

MIN

_

INDC

≈

-

-

-

μ

η

×

×

×

×

×

×

=

×

=

(3)

V

375

)

V

265

(

2

V

2

V

AC

AC

)

MAX

(

IN

DC

)

MAX

(

IN

=

×

=

×

=

(4)

mA

375

4

.

0

75

2

D

L

2

I

FL

FL

_

N

I

FL

_

ppk

=

×

=

×

=

(6)

mH

74

.

0

k

130

mA

375

4

.

0

90

f

I

D

V

L

s

FL

_

ppk

FL

MIN

_

INDC

p

≈

×

×

=

×

=

(7)

s

08

.

3

90

mA

375

mH

74

.

0

V

I

L

T

MIN

_

INDC

FL

_

ppk

p

FL

_

ON

μ

=

×

=

=

(8)

s

76

.

1

PF

100

%)

7

1

(

mH

73

.

0

14

.

3

2

C

L

2

T

MAX

_

DS

MAX

_

p

MAX

_

RINGING

μ

π

=

×

+

×

×

×

=

=

(9)

s

73

.

3

s

76

.

1

5

.

0

s

08

.

3

kHz

130

/

1

T

5

.

0

T

T

T

MAX

_

RINGING

FL

_

ON

SW

RST

μ

μ

μ

=

×

=

=

-

-

-

-

(10)

53

.

5

45

.

0

13

90

73

.

3

08

.

3

V

V

V

T

T

N

N

D

OUT

MIN

_

IN

RST

ON

S

P

=

+

×

=

+

×

=

(11)

37

.

1

45

.

0

13

45

.

0

18

V

V

'

V

V

N

N

D

OUT

D

DD

S

A

=

+

+

=

+

+

=

(12)

mA

75

75

.

0

90

5

V

P

I

MIN

_

INDC

FL

_

OUT

FL

_

IN

≈

×

=

×

=

η

(5)

Input Voltage Range

90VAC - 265VAC, 50/60Hz

5W

12V

0.4A

1.8A

System Efficiency CV,

η

0.75