Bluegiga Technologies Oy

Page 19 of 30

5 Design Guidelines

5.1 General Design Guidelines

LE113 can be used directly with a coin cell battery. Due to relatively high internal resistance of a coin cell

battery it is recommended to place a 100uF capacitor in parallel with the battery. The internal resistance of a

coin cell battery is initially in the range of 10 ohms but the resistance increases rapidly as the capacity is used.

Basically the higher the value of the capacitor the higher is the effective capacity of the battery and thus the

longer the life time for the application. The minimum value for the capacitor depends on the end application

and the maximum transmit power used. The leakage current of a 100uF capacitor is in the range of 0.5 uA to

3 uA and generally ceramic capacitors have lower leakage current than tantalum or aluminum electrolytic

capacitors.

Optionally TI’s TPS62730 can be used to reduce the current consumption during TX/RX and data processing

stages. TPS62730 is an ultra low power DC/DC converter with by-pass mode and will reduce the current

consumption during transmission nominally by ~20% when using 3V coin cell battery.

BLE113 Example Schematic

2 0 1 2 - 0 8 - 0 3

-

PR A

-

-

Blueg ig a Technolog ies Oy

-C1.0

1 5

REV:

SIZE:

CODE:

DRAWN:DATED:

DATED:

CHECKED:

QUAL ITY CONTROL :DATED:

DATED:

REL EASED:

COM PANY:

TITL E:

DRAWING NO:

SHEET:

OF

SCAL E:

REVISION RECORD

APPROVED:

ECO NO:

L TR

DATE:

1

2

3

4

5

6

D

C

B

A

C

D

B

A

PROGRAMMING INTERFACE

P1_0 and P1_1 req uire external pull-up or pull-down

resistor if config ured as inputs

C1 4

1 0 0 u F/1 6 V/1 0 % /TAN

1

STAT

2

SW

3

VIN

5

ON/BYP

6

VOUT

U5

TPS62730

L 1

2 .2

µH± 2 0 % , 1 30 m A, 0 .43 o hm

1

2

R4

NP

SW1

1

GND

2

GND

3

GND

4

GND

5

GND

6

GND

7

GND

8

AVDD

9

P2 _ 2

1 0

P2 _ 1

1 1

P2 _ 0

1 2

P1 _ 7

1 3

P1 _ 6

1 4

SCL

1 5

SDA

1 6

NC

1 7

DVDD

1 8

GND

2 5

GND

2 6

P0 _ 7

2 7

P0 _ 6

2 8

P0 _ 5

2 9

P0 _ 4

3 0

P0 _ 3

3 1

P0 _ 2

3 2

P0 _ 1

3 3

P0 _ 0

3 4

RESET

3 5

NC

3 6

GND

M OD2

BL E1 1 X_ P2

1

VDDIO

2

BYP

3

NC

4

SCL

5

GND

9

INT2

1 0

GND

1 1

INT1

1 2

GND

1 3

NC

U2

M M A8 4 5 1 Q

1

3

5

2

4

6

7 8

9 1 0

J 1

HEADER_ 2 X5 _ SM D_ 1 .2 7 M M

1

2

R2

1 0 K, 5 0 V, 0 .0 6 3 W

1

2

R2 1

1 0 K, 5 0 V, 0 .0 6 3 W

VBAT

P1 _ 7 /DCDC

2 V...3 V3 _ M OD

2 V...3 V3 _ M OD

P2 _ 2 /PROG

P2 _ 1 /PROG

P1 _ 7 /DCDC

SCL

SDA

2 V...3 V3 _ M OD

SCL

P2 _ 2 /PROG

2 V...3 V3 _ SW

P2 _ 1 /PROG

RESET_ N

2 V...3 V3 _ M OD

Figure 11: Example schematic for BLE113 with a coin cell battery, TPS62730 DCDC converter and an

I2C accelerometer

5.2 Layout Guide Lines

Use good layout practices to avoid excessive noise coupling to supply voltage traces or sensitive analog

signal traces. If using overlapping ground planes use stitching vias separated by max 3 mm to avoid emission

from the edges of the PCB. Connect all the GND pins directly to a solid GND plane and make sure that there

is a low impedance path for the return current following the signal and supply traces all the way from start to

the end.

A good practice is to dedicate one of the inner layers to a solid GND plane and one of the inner layers to

supply voltage planes and traces and route all the signals on top and bottom layers of the PCB. This

arrangement will make sure that any return current follows the forward current as close as possible and any

loops are minimized.