PM8803 datasheet(10/34 Pages) STMICROELECTRONICS

10 / 34 page

Pin descriptions and connection diagrams

PM8803

10/34

Doc ID 018559 Rev 2

9RTN2

Power ground for the secondary gate driver.

This pin is also connected to the drain of the internal current limiting power

MOSFET which closes VSS to the return path of the DC-DC converter.

This pin must be connected to RTN1 and ARTN

VSS

System low potential input.

Diode "OR'd" to the RJ45 connector and PSE's -48V supply, it is the more

negative input potential.

VDD

System high potential input.

The diode "OR" of several lines entering the PD, it is the most positive input

potential.

VDD

System high potential input.

The diode "OR" of several lines entering the PD, it is the most positive input

potential.

DET

Detection resistor pin.

Connect the signature resistance between the DET pin and VDD. Current

will flow through the resistor only during the detection phase.

This pin is 100V rated with negligible resistance with respect to the external

24.9K

Ω.

Front auxiliary startup pin.

Pulling up this pin to the auxiliary source will change the internal UVLO set-

tings and allow PD to be powered with voltage lower than nominal PoE volt-

ages. Default Inrush and DC current protection are active. Use a resistor

voltage divider from the auxiliary voltage to VSS to connect this low voltage

rating pin. Connect this pin to VSS if not used.

CLS

Classification resistor pin.

Connect the classification programming resistor from this pin to VSS.

DCCL

DC current limit.

A resistor between this pin and VSS will set the current limit for the interface

section of PM8803. It can be set to exceed the IEEE802.3at current limit.

Leave the pin open for standard IEEE 802.3at applications.

Rear Auxiliary startup pin.

Pulling up this pin will give high priority to an auxiliary power source like an

external wall adapter. Use a resistor voltage divider from the auxiliary volt-

age to ARTN to connect this low voltage rating pin.

Connect this pin to ARTN if not used.

Delay time set.

A resistor connected from this pin to ARTN sets the delay time between

GAT1 and GAT2. This pin cannot be left open.

FRS

Switching Frequency Set.

An external resistor connected from FRS to ARTN sets the oscillator fre-

quency.

Table 2.

Pin descriptions (continued)

Pin#

Name

Function

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