Error detection mode functionality

STP16DPPS05

18/35

DocID15817 Rev 3

7

Error detection mode functionality

7.1

Phase one: entering error detection mode

From the “normal mode” condition the device can switch to “error mode” by a logic

sequence on the OE/DM2 and LE/DM1 pins, as shown in the following table and diagram:

After these five CLK cycles, the device goes into “error detection mode” and at the rising

edge of the 6th CLK cycle, the SDI data are ready for sampling.

Table 13. Entering error detection mode - truth table

CLK

1°2°3°4°5°

OE/DM2

H

L

HHH

LE/DM1

LLL

H

L

Figure 18. Entering error detection mode - timing diagram

CLK

OE/DM2

LE/DM1