CLR [m].i

Clear bit of data memory

Description

The bit i of the specified data memory is cleared to 0.

Operation

[m].i

¬ 0

Affected flag(s)

TC2

TC1

TO

PD

OV

Z

AC

C

¾

¾

¾¾¾¾¾¾

CLR WDT

Clear Watchdog Timer

Description

The WDT is cleared (clears the WDT). The power down bit (PD) and time-out bit (TO) are

cleared.

Operation

WDT

¬ 00H

PD and TO

¬ 0

Affected flag(s)

TC2

TC1

TO

PD

OV

Z

AC

C

¾¾

00

¾¾¾¾

CLR WDT1

Preclear Watchdog Timer

Description

Together with CLR WDT2, clears the WDT. PD and TO are also cleared. Only execution of

this instruction without the other preclear instruction just sets the indicated flag which im-

plies this instruction has been executed and the TO and PD flags remain unchanged.

Operation

WDT

¬ 00H*

PD and TO

¬ 0*

Affected flag(s)

TC2

TC1

TO

PD

OV

Z

AC

C

¾¾

0*

0*

¾¾¾¾

CLR WDT2

Preclear Watchdog Timer

Description

Together with CLR WDT1, clears the WDT. PD and TO are also cleared. Only execution of

this instruction without the other preclear instruction, sets the indicated flag which implies

this instruction has been executed and the TO and PD flags remain unchanged.

Operation

WDT

¬ 00H*

PD and TO

¬ 0*

Affected flag(s)

TC2

TC1

TO

PD

OV

Z

AC

C

¾¾

0*

0*

¾¾¾¾

CPL [m]

Complement data memory

Description

Each bit of the specified data memory is logically complemented (1

¢s complement). Bits

which previously contained a 1 are changed to 0 and vice-versa.

Operation

[m]

¬ [m]

Affected flag(s)

TC2

TC1

TO

PD

OV

Z

AC

C

¾

¾

¾

¾

¾Ö¾

¾

HT48CA3

Rev. 1.40

21

July 16, 2003