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AT90PWM2 数据表(PDF) 29 Page - ATMEL Corporation |
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AT90PWM2 数据表(HTML) 29 Page - ATMEL Corporation |
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29 / 365 page  29 4317K–AVR–03/2013 AT90PWM2/3/2B/3B 7. System Clock 7.1 Clock Systems and their Distribution Figure 7-1 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to unused modules can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 41. The clock systems are detailed below. Figure 7-1. Clock Distribution AT90PWM2/3 General I/O Modules ADC CPU Core RAM clk I/O AVR Clock Control Unit clk CPU Flash and EEPROM clk FLASH clk ADC Source Clock Watchdog Timer Watchdog Oscillator Reset Logic Clock Multiplexer Watchdog Clock Calibrated RC Oscillator (Crystal Oscillator) External Clock PSC0/1/2 PLL CLK PLL |
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