1-408

Parameter

Symbol

Device

Min.

Typ.

Max.

Unit

Test Conditions

Fig.

Note

Propagation

t

PHL

HCPL-7100

70

ns

7, 8

5, 6

Delay Time

CMOS Signal Levels

to Logic

HCPL-7101

28

40

Low Output

HCPL-7100

70

ns

C

TTL Signal Levels

HCPL-7101

40

Propagation

t

PLH

HCPL-7100

70

ns

C

7, 8

5, 6

Delay Time

CMOS Signal Levels

to Logic

HCPL-7101

27

40

High Output

HCPL-7100

70

ns

C

TTL Signal Levels

HCPL-7101

40

Pulse Width

PWD

HCPL-7100

20

ns

C

7, 9

6, 7

Distortion

CMOS Signal Levels

HCPL-7101

2

6

HCPL-7100

20

ns

C

TTL Signal Levels

HCPL-7101

6

Data Rate

HCPL-7100

15

MBd

% PWD < 30%

8

HCPL-7101

50

65

Propagation

t

PSK

HCPL-7101

10

ns

10

9

Delay Skew

Output Rise

t

R

HCPL-7100

12

ns

7

Time

CMOS Signal Levels

(10-90%)

HCPL-7101

10

Output Fall

t

F

HCPL-7100

8

ns

C

7

Time

CMOS Signal Levels

(90-10%)

HCPL-7101

7

Random Jitter

RJ

HCPL-7101

50

ps rms

V

f = 25 MHz, input rise/

fall time = 5 ns.

R

TTL Threshold Levels.

Propagation

13

ns

12

6

Delay Time From

CMOS Signal Levels

Output Enabled

to Logic High

12

ns

C

Output

TTL Signal Levels

Propagation

t

PZL

11

ns

12

6

Delay Time From

CMOS Signal Levels

Output Enabled

to Logic Low

10

ns

C

Output

TTL Signal Levels

Switching Specifications

Guaranteed across recommended operating conditions. Test conditions represent worst case values for the

parameter under test. Test conditions that are not specified can be anywhere within their operating range. All

typicals are at 25

°C and 5 V supplies unless otherwise noted.