HCPL-7101 datasheet(9/14 Pages) HP

9 / 14 page

1-410

Notes:

1. The LED is OFF when the VI is high and ON when VI is low.

2. Device considered a two terminal device; pins 1-4 shorted together and pins 5-8 shorted together.

3. In accordance with UL 1577, for devices with minimum VISO specified at 3750 V rms, each optocoupler is proof-tested by applying an

insulation test voltage greater than 4500 V rms for one second (leakage current detection limit II-O < 5 µA). This test is performed

before the method b, 100% production test for partial discharge shown in the VDE 0884 Insulation Characteristics Table.

4. CI is the capacitance measured at pin 2 (VI).

5. tPHL propagation delay is measured from the 50% level on the falling edge of the VI signal to the logic switching level of the VO signal.

tPLH propagation delay is measured from the 50% level on the rising edge of the VI signal to the logic switching level of the VO signal.

6. The logic switching levels are 1.5 V for TTL signals (0-3 V) and 2.5 V for CMOS signals (0-5 V).

7. PWD is defined as |tPHL - tPLH|. %PWD (percent pulse width distortion) is equal to PWD in ns divided by symbol duration (bit length)

in ns.

8. Minimum data rate is calculated as follows: %PWD/PWD where %PWD is typically chosen by the design engineer (30% is common).

9. tPSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at the same temperature, supply voltage,

and output load within the recommended operating condition range.

10. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VO > 3.2 V. CML is the maximum

common mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common mode voltage slew rates apply to

both rising and falling common mode voltage edges.

11. Unloaded dynamic power dissipation is calculated as follows: CPD • VDD2 • f + IDD • VDD where f is switching frequency in MHz.

Figure 1. Recommended Application Circuit.

Figure 2. Recommended Printed Circuit Board Layout.

HCPL-7101 数据表(PDF) 9 Page - Agilent(Hewlett-Packard)