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Atmel | SMART SAM R21 [PRELIMINARY DATASHEET SUMMARY]

Atmel-42223AS–SAM-R21_Summary–07/2014

7.

Processor And Architecture

7.1

Cortex M0+ Processor

processor, and upward compatible to Cortex-M3 and M4 processors.

7.1.1

Cortex M0+ Configuration

Note:

1. All software run in privileged mode only

The ARM Cortex-M0+ core has two bus interfaces:

memory, including flash and RAM

Single 32-bit I/O port bus interfacing to the PORT with one-cycle loads and stores

Features

Configuration option

Atmel | SMART SAM R21

configuration

Interrupts

External interrupts 0-32

32

Data endianness

Little-endian or big-endian

Little-endian

SysTick timer

Present or absent

Present

Number of watchpoint comparators

0, 1, 2

2

Number of breakpoint comparators

0, 1, 2, 3, 4

4

Halting debug support

Present or absent

Present

Multiplier

Fast or small

Fast (single cycle)

Single-cycle I/O port

Present or absent

Present

Wake-up interrupt controller

Supported or not supported

Not supported

Vector Table Offset Register

Present or absent

Present

Unprivileged/Privileged support

Present or absent

Absent(1)

Memory Protection Unit

Not present or 8-region

Not present

Reset all registers

Present or absent

Absent

Instruction fetch width

16-bit only or mostly 32-bit

32-bit