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STPMS1 数据表(PDF) 6 Page - STMicroelectronics

部件名 STPMS1
功能描述  Dual-channel 1-bit, 2 MHz, 1st order Dual-channel 1-bit, 2 MHz, 1st order
PDF  23 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STPMS1 数据表(HTML) 6 Page - STMicroelectronics

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General operating conditions
STPMS1
6/23
Doc ID 16524 Rev 2
4
General operating conditions
VCC = 5 V, TA = 25 °C, 2.2 µF between VDD and GND, 100 nF between VCC and GND,
fCLK = 2.048 MHz unless otherwise specified.
Table 5.
General operating conditions
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
General section
VCC
Operating supply voltage
3.165
5.5
V
ICC
Quiescent current
1.049 MHz; VCC=3.165 V; CL=100 nF, no
loads
2.5
mA
VPOR
Power on reset on VCC
2.5
V
VDD
Regulated supply voltage 1.049 MHz; VCC=3.2 V; CL=100 nF, no loads
2.85
3.00
3.15
V
ILATCH
Current injection latch-up
immunity
300
mA
fCLK
Nominal frequencies
1.0
2.458
MHz
DC measurement accuracy
Resolution
11
16
bit
INL
Integral non-linearity
Result referred to a 13-bit resolution of CIP-
CIN channel
0.35
LSB
Result referred to a 9-bit resolution of VIP-
VIN channel
0.5
DNL
Differential linearity
Result referred to a 13-bit resolution of CIP-
CIN channel
0.2
LSB
Result referred to a 9-bit resolution of VIP-
VIN channel
0.4
Offset error
Result referred to a 13-bit resolution of CIP-
CIN channel
0.15
LSB
Result referred to a 9-bit resolution of VIP-
VIN channel
0.05
Gain error
Result referred to a 13-bit resolution of CIP-
CIN channel
0.05
LSB/
µV
Result referred to a 9-bit resolution of VIP-
VIN channel
0.001
NF
Noise floor
CIP-CIN channel, Gain 8x
115
dB
PSRRDC
Power supply DC
rejection
Voltage signal: 200 mVrms/50 Hz
Current signal: 10 mVrms/50 Hz
fCLK= 2.048 MHz
VCC=3.3 V±10 %, 5 V±10 %
0.2
%



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