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STPMS1 数据表(PDF) 8 Page - STMicroelectronics |
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STPMS1 数据表(HTML) 8 Page - STMicroelectronics |
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8 / 23 page ![]() General operating conditions STPMS1 8/23 Doc ID 16524 Rev 2 CLK - clock signal on CLK pin CLKsample - sigma-delta sample frequency bsV - sigma-delta bitstream of voltage signal bsC - sigma-delta bitstream of current signal DATA - multiplexed data of voltage and current signal on DAT pin Symbol Parameter Test conditions Min. Typ. Max. Unit VOH Output high voltage IO=-1 mA, CL=50 pF, VCC=3.2 V VCC- 0.4 V VOL Output low voltage IO=+1 mA, CL=50 pF, VCC=3.2 V 0.4 V IUP Pull up current 15 µA tTR Transition time CLOAD=50 pF 10 ns tL Latency From 50 % of CLK to 50 % to DAT 40 ns Clock input fCLK Nominal frequencies Low precision 1.0 1.228 MHz High precision 2.0 2.458 MHz On chip reference voltage VREF Reference voltage 1.21 1.23 1.25 V TC Temperature coefficient After calibration 30 50 ppm/ °C Table 5. General operating conditions (continued) Figure 3. Timing diagram AM07832v1 AM07832v1 |
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