GMS81C2012 datasheet(72/92 Pages) HYNIX

72 / 92 page

GMS81C2020/GMS81C2120

Hyundai Micro Electro nics

preliminary

Nov. 1999 Ver 0.0

20. WATCHDOG TIMER

The purpose of the watchdog timer is to detect the mal-

function (runaway) of program due to external noise or

other causes and return the operation to the normal condi-

tion.

The watchdog timer has two types of clock source.

The first type is an on-chip RC oscillator which does not

require any external components. This RC oscillator is sep-

arate from the external oscillator of the Xin pin. It means

that the watchdog timer will run, even if the clock on the

Xin pin of the device has been stopped, for example, by en-

tering the STOP mode.

The other type is a prescaled system clock.

The watchdog timer consists of 7-bit binary counter and

the watchdog timer data register. When the value of 7-bit

binary counter is equal to the lower 7 bits of WDTR, the

interrupt request flag is generated. This can be used as

WDT interrupt or reset the CPU in accordance with the bit

WDTON .

Note: Because the watchdog timer counter is enabled af-

ter clearing Basic Interval Timer, after the bit WD-

TON set to "1", maximum error of timer is depend on

prescaler ratio of Basic Interval Timer.

The 7-bit binary counter is cleared by setting WDTCL(bit7

of WDTR) and the WDTCL is cleared automatically after

1 maching cycle.

The RC oscillated watchdog timer is activated by setting

the bit RCWDT as shown below.

The RCWDT oscillation period is vary with temperature,

VDD and process variations from part to part (approxi-

mately, 40~120uS ). The following equation shows the

RCWDT oscillated watchdog timer time-out.

T RC W D T=C L K RC W D T×28×[W D TR .6~0]+ (C LK RCW D T×28)/2

wh ere, CL K RCW D T = 40~ 120uS

In addition, this watchdog timer can be used as a simple 7-

bit timer by interrupt WDTIF. The interval of watchdog

timer interrupt is decided by Basic Interval Timer. Interval

equation is as below.

TWDT = [WDTR.6~0] ×

××× Interval of BIT

Figure 20-1 Block Diagram of Watchdog Timer

LDM

CKCTLR,#3FH; enable the RC-osc WDT

LDM

WDTR,#0FFH; set the WDT period

STOP

; enter the STOP mode

NOP

; RC-osc WDT running

Basic Interval Timer

Interrupt

Watchdog Timer

BITIF

7-bit Counter

WDTR (7-bit)

OFD

WDTCL

WDTON

Interrupt Request

To RESET

Clock Control Register

CKCTLR

ADDRESS : ECH

RESET VALUE : -0010111

WAKEUP RCWDT

WDTON

BTCL

BTS2

BTS1

BTS0

XXXX

Watchdog Timer Register

WDTR

ADDRESS : EDH

RESET VALUE : 01111111

WDTCL

7-bit Watchdog Counter Register

Overflow Detection

Bit Manipulation Not Available

WDTCL

RESET

÷ 8

÷ 16

÷ 128

÷ 256

÷ 512

÷1024

÷ 32

÷ 64

MUX

fXI

BITR (8-BIT)

BTS[2:0]

RCWDT

Internal RC OSC

BTCL

Clear

WAKEUP

STOP

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