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HMS81032TL 数据表(PDF) 77 Page - Hynix Semiconductor |
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HMS81032TL 数据表(HTML) 77 Page - Hynix Semiconductor |
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77 / 77 page ![]() APPENDIX lxxviii JUNE 2001 Ver 1.00 Control Operation & Etc. No. Mnemonic Op Code Byte No Cycle No Operation Flag NVGBHIZC 1 BRK 0F 1 8 Software interrupt : B ← ”1”, M(sp) ← (pcH), sp ←sp-1, M(s) ← (pcL), sp ← sp - 1, M(sp) ← (PSW), sp ← sp -1, pcL ← ( 0FFDEH ) , pcH ← ( 0FFDFH) . ---1-0-- 2 DI 60 1 3 Disable all interrupts : I ← “0” -----0-- 3 EI E0 1 3 Enable all interrupt : I ← “1” -----1-- 4 NOP FF 1 2 No operation -------- 5 POP A 0D 1 4 sp ← sp + 1, A ← M( sp ) 6 POP X 2D 1 4 sp ← sp + 1, X ← M( sp ) -------- 7 POP Y 4D 1 4 sp ← sp + 1, Y ← M( sp ) 8 POP PSW 6D 1 4 sp ← sp + 1, PSW ← M( sp ) restored 9 PUSH A 0E 1 4 M( sp ) ← A , sp ← sp - 1 10 PUSH X 2E 1 4 M( sp ) ← X , sp ← sp - 1 -------- 11 PUSH Y 4E 1 4 M( sp ) ← Y , sp ← sp - 1 12 PUSH PSW 6E 1 4 M( sp ) ← PSW , sp ← sp - 1 13 RET 6F 1 5 Return from subroutine sp ← sp +1, pcL ← M( sp ), sp ← sp +1, pcH ← M( sp ) -------- 14 RETI 7F 1 6 Return from interrupt sp ← sp +1, PSW ← M( sp ), sp ← sp + 1, pcL ← M( sp ), sp ← sp + 1, pcH ← M( sp ) restored 15 STOP EF 1 3 Stop mode ( halt CPU, stop oscillator ) -------- |
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