STAC9704 datasheet(13/49 Pages) HYNIX

13 / 49 page

SigmaTel, Inc.

STAC9704/7

10/02/98

•

PCM Playback

2 output slots

2 Channel composite PCM output stream

•

PCM Record data

2 input slots

2 Channel composite PCM input stream

•

Control

2 output slots

Control register write port

•

Status

2 input slots

Control register read port

Synchronization of all AC-link data transactions is signaled by the AC’97 controller.

The

STAC9704/7 drives the serial bit clock onto AC-link. The AC’97 controller then qualifies with a

synchronization signal to construct audio frames.

SYNC, fixed at 48 kHz, is derived by dividing down the serial bit clock (BIT_CLK). BIT_CLK, fixed

at 12.288 MHz, provides the necessary clocking granularity to support 12, 20-bit outgoing and incoming

time slots. AC-link serial data is transitioned on each rising edge of BIT_CLK. The receiver of AC-

link data, STAC9704/7 for outgoing data and AC’97 controller for incoming data, samples each serial

bit on the falling edges of BIT_CLK.

The AC-link protocol provides for a special 16-bit (13-bits defined, with 3 reserved trailing bit

positions) time slot (Slot 0) wherein each bit conveys a valid tag for its corresponding time slot within

the current audio frame. A “1” in a given bit position of slot 0 indicates that the corresponding time

slot within the current audio frame has been assigned to a data stream, and contains valid data. If a slot

is “tagged” invalid, it is the responsibility of the source of the data, (STAC9704/7 for the input stream,

AC’97 controller for the output stream), to stuff all bit positions with 0’s during that slot’s active time.

SYNC remains high for a total duration of 16 BIT_CLKs at the beginning of each audio frame. The

portion of the audio frame where SYNC is high is defined as the “Tag Phase”. The remainder of the

audio frame where SYNC is low is defined as the “Data Phase”.

Additionally, for power savings, all clock, sync, and data signals can be halted.

Figure 5. AC’97 Standard Bi-directional Audio Frame

OUTGOING STREAMS

INCOMING STREAMS

SYNC

SLOT #

TAG PHASE

11 12

TAG

CMD

ADR

CMD

DATA

PCM

LEFT

PCM

RSVD

RSVD RSVD RSVD RSVD RSVD

RSVD

PCM

LEFT

PCM

STATUS

DATA

STATUS

ADR

TAG

DATA PHASE

STAC9704 数据表(PDF) 13 Page - Hynix Semiconductor

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