Pin Descriptions - ICS1572-101

PIN#

NAME

DESCRIPTION

13

CLK+

Clock out (non-inverted)

12

CLK

−

Clock out (inverted)

8

LOAD

Load output. This output is normally at the CLK frequency divided by N1.

3

XTAL1

Quartz crystal connection 1/external reference frequency input

4

XTAL2

Quartz crystal connection 2

2

AD0

Address/Data Bit 0 (LSB)

19

AD1

Address/Data Bit 1

18

AD2

Address/Data Bit 2

17

AD3

Address/Data Bit 3 (MSB)

9

LD/N2

Divided LOAD output. See text.

5

STROBE

Control for address/data latch

16

VDD

PLL system power (+5V. See application diagram.)

15

VDDO

Output stage power (+5V)

14

IPRG

Output stage current set

6,7

VSS

Device ground. Both pins must be connected to the same ground potential.

1,10,11,20

NC

Not connected

Pin Descriptions - ICS1572-301

PIN#

NAME

DESCRIPTION

13

CLK+

Clock out (non-inverted)

12

CLK

−

Clock out (inverted)

8

LOAD

Load output. This output is normally at the CLK frequency divided by N1.

3

XTAL1

Quartz crystal connection 1/external reference frequency input

4

XTAL2

Quartz crystal connection 2

5

DATCLK

Data Clock (Input)

19

DATA

Serial Register Data (Input)

18

HOLD~

HOLD (Input)

17

BLANK

Blanking (Input). See Text.

9

LD/N2

Divided LOAD output/shift clock. See text.

2

EXTFBK

External feedback connection for PLL (input). See text.

16

VDD

PLL system power (+5V. See application diagram.)

15

VDDO

Output stage power (+5V)

14

IPRG

Output stage current set

6,7

VSS

Device ground. Both pins must be connected.

1,10,11,20

NC

Not connected

ICS1572

13