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ICS1572 数据表(PDF) 11 Page - Integrated Circuit Systems |
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ICS1572 数据表(HTML) 11 Page - Integrated Circuit Systems |
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11 / 19 page ![]() BIT(S) BIT REF. DESCRIPTION 33-38 M[0]..M[5] M counter control bits Modulus = value +1 39 RESERVED Set to zero. 40 DBLFREQ Doubles modulus of dual-modulus prescaler (from 6/7 to 12/14). 41-44 A[0]..A[3] Controls A counter. When set to zero, modulus=7. Otherwise, modulus=7 for “value” underflows of the prescaler, and modulus=6 thereafter until M counter underflows. 45-48 RESERVED Set to zero. 49-55 R[0]..R[6] Reference divider modulus control bits Modulus = value + 1 56 RESERVED Set to zero. ICS1572 11 |
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