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ICS1574B 数据表(PDF) 7 Page - Integrated Circuit Systems

部件名 ICS1574B
功能描述  User Programmable Laser Engine Pixel Clock Generator
PDF  12 Pages
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制造商  ICST [Integrated Circuit Systems]
网页  http://www.icst.com
标志 ICST - Integrated Circuit Systems

ICS1574B 数据表(HTML) 7 Page - Integrated Circuit Systems

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7
ICS1574B
]
3
[
K
L
C
P]
2
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1
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0
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3
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1
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1
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11
5
01
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6
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8
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1X
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Register Mapping — ICS1574B
NOTE: It is not necessary to understand the function of these bits to use the ICS1574B. PC Software is available from ICS to
automatically generate all register values based on requirements. Contact factory for details.
BIT(S)
BIT REF.
DESCRIPTION
1 – 4
PCLK[0]..PCLK[3]
Sets PCLK divider modulus according to this table.
These bits are set to implement a divide-by-four on power-up.
(X = Don't Care)
5, 6
Reserved
Must be set to 0.
7
Reserved
Must be set to 1.
8
SELXTAL
Normally set to 0. When set to logic 1, passes the reference
frequency to the post-scaler instead of the PLL output
(defaults to 1 on power-up).
9
Reserved
Must be set to 0.
10
Reserved
Must be set to 1.
11, 12
Reserved
Must be set to 0.
13 – 14
S[0]..S[1]
PLL post-scaler / test mode select bits.



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