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ICS1574B 数据表(PDF) 9 Page - Integrated Circuit Systems |
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ICS1574B 数据表(HTML) 9 Page - Integrated Circuit Systems |
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9 / 12 page ![]() 9 ICS1574B BIT(S) BIT REF. DESCRIPTION 45 Reserved Must be set to 1. 46 PCLK_EN Must be set to 0. Disables the PCLK divider when set to 1 regardless of PCLKEN input state. 47, 48 Reserved Must be set to 0. 49 – 55 R[0]..R[6] Reference divider modulus control bits. Modulus = value +1. 56 REF_POL PLL locks to rising edge of XTAL1 input when REFPOL = 1, falling edge of XTAL1 when REFPOL = 0. |
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