Integrated

Circuit

Systems, Inc.

General Description

Features

ICS1886

Block Diagram

PHYceiver is a trademark of Integrated Circuit Systems, Inc.

ICS1886RevC120996

•

Data and clock recovery for: 32.064 Mb/s (Japan)

34.368 Mb/s (Europe - E3) 125 MHz (Ethernet)

139.264 Mb/s (Europe - E4)

•

Clock multiplication from either a crystal, differential

or single-ended timing source

•

Continuous clock in the absence of data

•

No external PLL components

•

Lock/Loss status indicator output

•

Loopback mode for system diagnostics

•

Selectable loop timing mode

•

PECL drivers with settable sink current

The ICS1886 is designed to provide high performance clock

recovery and generation for either 32.064 Mb/s, 34.368

Mb/s, 125 Mb/s or 139.264 Mb/s NRZ or NRZI serial data

streams. The ICS1886 is ideally suited for LAN transceiver

applications in either European or Japanese communication

environments.

The ICS1886 also operates at the 100Mbit Ethernet

frequency of 125 MHz. This is ideal for serial Ethernet data

applications where no serial to parallel conversion is

required.

Clock and data recovery is performed on an input serial data

stream or the buffered transmit data depending upon the state

of the loopback input. A continuous clock source will

continue to be present even in the absence of input data. All

internal timing is derived from either a low cost crystal or an

external clock module.

The ICS1886 utilizes advanced CMOS phase-locked loop

technology which combines high performance and low

power at a greatly reduced cost.

Pin Configuration

28-Pin SOIC