 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
ICS1892 数据表(PDF) 97 Page - Integrated Circuit Systems |
|
|
|||||||||||||||||||||||||||||
ICS1892 数据表(HTML) 97 Page - Integrated Circuit Systems |
|
|
97 / 148 page  Chapter 8 Management Register Set ICS1892, Rev. D, 2/26/01 February 26, 2001 97 ICS1892 © 2000-2001, Integrated Circuit Systems, Inc. All rights reserved. 8.13.8 Link Loss Inhibit (bit 18.1) The Link Loss Inhibit bit allows an STA to prevent the ICS1892 from dropping the link in 10Base-T mode. When an STA sets this bit to logic: • Zero, the state machine behaves normally and the link status is based on the signaling detected Twisted- Pair Receiver inputs. • One, the ICS1892 10Base-T Link Integrity Test state machine is forced into the ‘Link Passed’ state regardless of the Twisted-Pair Receiver input conditions. 8.13.9 Squelch Inhibit (bit 18.0) The Squelch Inhibit bit allows an STA to control the ICS1892 Squelch Detection in 10Base-T mode. When an STA sets this bit to logic: • Zero, before the ICS1892 can establish a valid link, the ICS1892 must receive valid 10Base-T data. • One, before the ICS1892 can establish a valid link, the ICS1892 must receive both valid 10Base-T data followed by an IDL. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
