ICS2572 datasheet(2/10 Pages) ICST

2 / 10 page

Pin Configuration

XTAL1

VDD

XTAL2

CLK+

XTFREQ

CLK-

FS0

VSS

FS1

LOAD

STROBE

VAA

FS2

VSS

FS3

VDD

MS0

MCLK

VSS

MS1

Pin Descriptions

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

XTAL1

Quartz crystal connection 1/Reference Frequency Input.

XTAL2

Quartz crystal connection 2.

EXTFREQ

External Frequency Input

FS0

VCLK PLL Frequency Select LSB.

FS1

VCLK PLL Frequency Select Bit.

FS2

VCLK PLL Frequency Select Bit.

FS3

VCLK PLL Frequency Select MSB.

STROBE

Control for Latch of VCLK Select Bits (FS0-FS3).

MS0

MCLK PLL Frequency Select LSB.

MS1

MCLK PLL Frequency Select MSB.

CLK+

Pixel Clock Output (not inverted)

CLK-

Pixel Clock Output (inverted)

LOAD

Divided Dotclock (/4, 5, or 8)

MCLK

MCLK Frequency Output

RESERVED

Must Be Connected to VSS.

10, 14

VSS

Device Ground. All pins must be connected.

13, 20

VDD

Output Stage Vdd. All pins must be connected.

VAA

Synthesizer Vdd.

20-Pin DIP or SOIC

J-4, J-7

ICS2572

E-96

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