Frequency Synthesizer Description

Refer to Figure 1 for a block diagram of the ICS2572.

The ICS2572 generates its output frequencies using phase-

locked loop techniques. The phase-locked loop (or PLL) is a

closed-loop feedback system that drives the output frequency

to be ratiometrically related to the reference frequency pro-

vided to the PLL. The phase-frequency detector shown in the

block diagram drives the VCO to a frequency that will cause

the two inputs to the phase-frequency detector to be matched

in frequency and phase. This occurs when:

N

2

where N is the effective modulus of the feedback divider chain

and R is the modulus of the reference divider chain.

The feedback divider on the ICS2572 may be set to any integer

value from 257 to 512. This is done by the setting of the N0-N7

bits. The standard reference divider on the ICS2572 is fixed to

a value of 43 (this may be set to a different value via ROM

programming; contact factory). The ICS2572 is equipped with

a post-divider and multiplexer that allows the output frequency

range to be scaled down from that of the VCO by a factor of 2,

4, or 8.

Therefore, the VCO frequency range will be from 5.976 to

11.906 (257/43 to 512/43) of the reference frequency. The

output frequency range will be from 0.747 to 11.906 times the

reference frequency. Worst case accuracy for any desired fre-

quency within that range will be 0.2%.

If a 14.31818 MHz reference is used, the output frequency

range would be from 10.697 MHz to 170.486 MHz.

Programming Example

Suppose that we want differential CLK o utput to be

45.723 MHz. We will assume the reference frequency to be

14.31818 MHz.

The VCO frequency range will be 85.565 MHz to

170.486 MHz (5.976 * 14.31818 to 11.906 * 14.31818). We

will need to set the post-divider to two to get an output of

45.723 MHz.

The VCO will then need to be programmed to two times

45.723 MHz, or 91.446 MHz. To calculate the required feed-

back divider modulus we divide the VCO frequency by the

reference frequency and multiply by the reference divider:

91.446

*43=274.62

14.31818

which we round off to 275. The exact output frequency will

be:

275

1

*14.31818*

=45.784 MHz

43

2

The value of the N programming bits may be calculated by

subtracting 257 from the desired feedback divider modulus.

LOAD Frequency Selection

The LOAD (or divided dotclock) output frequency will be the

CLK+/CLK- frequency divided by 1, 4, 5, or 8. The choice of

modulus is a factory option, and is specified along with the

ROM frequencies in the VCLK and MCLK tables by way of

the two-digit suffix of the part number.

Reference Oscillator & Crystal

Selection

The ICS2572 has on-board circuitry to implement a Pierce

oscillator with the addition of only one external component, a

quartz crystal. Pierce oscillators operate the crystal in parallel-

resonant (also called anti-resonant mode. See the AC Charac-

teristics for the effective capacitive loading to specify when

ordering crystals.

Crystals characterized for their series-resonant frequency may

also be used with the ICS2572. Be aware that the oscillation

frequency in circuit will be slightly higher than the frequency

that is stamped on the can (typically 0.025-0.05%).

As the entire operation of the phase-locked loop depends on

having a stable reference frequency, we recommend that the

crystal be mounted as closely as possible to the package. Avoid

routing digital signals or the ICS2572 outputs underneath or

near these traces. It is also desirable to ground the crystal can

to the ground plane, if possible.

ICS2572

E-99