ICS307

Serially Programmable Clock Source

MDS 307 D

4

Revision 042501

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel •www.icst.com

Setting the Device Characteristics

The tables below show the settings which can be configured, in addition to the VCO and Reference dividers.

CLK1

Maximum

Max. Freq.

S2

S1

S0

Industrial

Version

0

0

0

10

40

36

0

0

1

2

200

180

0

1

0

8

50

45

0

1

1

4

100

90

1

0

0

5

80

72

1

0

1

7

55

50

1

1

0

3

135

120

1

1

1

6

67

60

Table 1. Output Divide and

Maximum Output Frequency

Table 2. CLK2 Output

TTL

Duty cycle measured at

Recommended VDD

0

1.4V

5 V

1

VDD/2

3.3 V

Table 3. Output Duty Cycle Configuration

C1

C0

VDD = 5 V

VDD = 3.3 V

0

0

22.3 - 0.083 f

22.1 - 0.094 f

0

1

23.1 - 0.093 f

22.9 - 0.108 f

1

0

23.7 - 0.106 f

23.5 - 0.120 f

1

1

24.4 - 0.120 f

24.2 - 0.135 f

Table 4. Crystal Load Capacitance

Note: f is the crystal frequency, between 10 and

27 MHz. Effective load capacitance will be higher

for crystal frequencies lower than 10 MHz. If a

clock input is used, set C1 = 0 and C0 = 0.

Note: The TTL bit optimizes the duty cycle at

different VDD. When VDD is 5 V, set to 0

for a near-50% duty cycle with TTL levels.

When VDD is 3.3 V, set this bit to a 1, so the

50% duty cycle is achieved at VDD/2.

F1

F0

CLK2

0

0

REF

0

1

REF/2

1

0

OFF (Low)

1

1

CLK1/2

0 = Connect directy to ground

1 = Connect directly to VDD