ICS307

Serially Programmable Clock Source

MDS 307 D

6

Revision 042501

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126•(408) 295-9800tel •www.icst.com

External Components / Crystal Selection

The ICS307 require a 0.01µF decoupling capacitor to be connected between VDD and GND. It must be

connected close to the ICS307 to minimize lead inductance. A 33

Ω terminating resistor can be used in

series with the CLK1 and CLK2 outputs. A parallel resonant, fundamental mode crystal with a load

(correlation) capacitance of C should be used, where C is the value calculated from Table 4. For crystals

with a specified load capacitance greater than C, additional crystal capacitors may be connected from each

of the pins X1 and X2 to Ground as shown in the Block Diagram on page 1. The value (in pF) of these

crystal caps should be = (CL-C)*2, where CL is the crystal load capacitance in pF. These external

capacitors are only required for applications where the exact frequency is critical. For a clock input,

connect to X1 and leave X2 unconnected (no capacitors on either pin).

Figure 2. Timing Diagram for Programming the ICS307

Parameter

Condition

Min

Max

Units

Setup time.

10

ns

Hold time after SCLK.

10

ns

Data wait time.

10

ns

Strobe pulse width

40

ns

AC Parameters for Writing to the ICS307

DATA

C1

C0

TTL

F1

R1

R0

•

•

•

•

•

•

SCLK

STROBE

tsetup

thold

tw

ts