S1

S0

CLK

Multiplier

Accuracy

0

0

Power Down CLK

-

-

0

1

25

1.746

1 ppm

M

0

33.33

2.328

0.008%

M

1

40

2.794

1 ppm

1

0

50

3.492

1 ppm

1

1

66.66

4.656

0.008%

ICS514

LOCO™ PLL Clock Generator

MDS 514 B

2

Revision 080699

Printed 11/13/00

Integrated Circuit Systems • 525 Race Street • San Jose•CA • 95126 • (408)295-9800tel• (408)295-9818fax

Pin Assignment

18

2

3

4

7

6

5

X1/ICLK

VDD

GND

REF

X2

S1

S0

CLK

Number

Name

Type

Description

1

X1/ICLK

I

Crystal connection to 14.31818 MHz crystal or clock input.

2

VDD

P

Connect to +3.3V or +5V.

3

GND

P

Connect to ground.

4

REF

O

Reference 14.31818 MHz crystal oscillator buffered clock output.

5

CLK

O

Clock output per table above.

6

S0

T I

Select 0 for output clock. Connect to GND or VDD or float. See table above.

7

S1

T I

Select 1 for output clock. Connect to GND or VDD or float. See table above.

8

X2

O

Crystal connection to 14.31818 MHz crystal. Leave unconnected for clock input.

Pin Descriptions

Key: I = Input, TI = Tri-Level Input, O = output, P = power supply connection

Clock Decoding Table (MHz) with

14.31818MHz Crystal or Clock Input

0 = connect directly to ground.

1 = connect directly to VDD.

M = leave unconnected (floating).

CLK and REF stop low in power down state.

Notes: 1. With S1 = S0 = 0, the internal PLL is turned off and the CLK output stops low.

The crystal oscillator and REF output are still active.

2. With a clock input, the phase relationship between the input and output clocks can

change each time the device is powered on. If a fixed phase relationship is required,

please use our ICS571 or other zero delay multipliers.