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ICS525-01RT 数据表(PDF) 2 Page - Integrated Circuit Systems |
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ICS525-01RT 数据表(HTML) 2 Page - Integrated Circuit Systems |
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2 / 8 page ![]() ICS525-01/02 OSCaR™ User Configurable Clock MDS 525-01/02 I 2 Revision 071100 Printed 11/13/00 Integrated Circuit Systems, Inc. • 525 Race Street •San Jose• CA • 95126•(408) 295-9800tel• www.icst.com ICS525-01 Pin Descriptions Pin # Name Type Description 1, 2, 24-28 R5, R6, R0-R4 I(PU) Reference divider word input pins determined by user. Forms a binary number from 0 to 127. 3, 4, 5 S0, S1, S2 I(PU) Select pins for output divider determined by user. See table on page 3. 6, 23 VDD P Connect to VDD. 7 X1/ICLK X1 Crystal connection. Connect to a parallel resonant fundamental crystal, or input clock. 8 X2 X2 Crystal connection. Connect to a crystal, or leave unconnected for clock. 9, 20 GND P Connect to ground. 10-18 V0-V8 I(PU) VCO divider word input pins determined by user. Forms a binary number from 0 to 511. 19 PD I(PU) Power Down. Active low. Turns off entire chip when low. Clock outputs stop low. 21 CLK O Output Clock determined by status of R0-R6, V0-V8, S0-S2 and input frequency. 22 REF O Reference output. Buffered crystal oscillator (or clock) output. ICS525-01 ICS525-02 Key: I(PU) = Input with internal pull-up resistor; X1, X2 = Crystal connections; O = Output; P = Power supply connection ICS525-02 Pin Descriptions Pin # Name Type Description 1, 2, 24-28 R5, R6, R0-R4 I(PU) Reference divider word input pins determined by user. Forms a binary number from 0 to 127. 3, 4, 5 S0, S1, S2 I(PU) Select pins for output divider determined by user. See table on page 3. 6, 23 VDD P Connect to VDD. 7 X1/ICLK X1 Crystal connection. Connect to a parallel resonant fundamental crystal, or input clock. 8 X2 X2 Crystal connection. Connect to a crystal, or leave unconnected for clock. 9, 20 GND P Connect to ground. 10-18 V0-V8 I(PU) VCO divider word input pins determined by user. Forms a binary number from 0 to 511. 19 PDTS I(PU) Power Down and Tri-state. Active low. Turns off entire chip and tri-states the outputs when low. 21 CLK O Output Clock determined by status of R0-R6, V0-V8, S0-S2 and input frequency. 22 REF O Reference output. Buffered crystal oscillator (or clock) output. R4 S2 X1/ICLK PD R0 VDD GND R1 VDD REF CLK 1 8 9 2 3 4 5 6 7 10 11 12 13 14 16 15 20 17 18 19 25 24 23 22 21 26 27 28 V2 X2 V4 GND R2 V8 R3 V6 V5 R5 R6 V0 V3 V1 S0 S1 V7 R4 X2 VDD X1/ICLK GND REF CLK PDTS 1 8 9 2 3 4 5 6 7 10 11 12 13 14 16 15 20 17 18 19 25 24 23 22 21 26 27 28 V2 V4 VDD GND R2 V8 R3 R1 V6 V5 R0 R5 R6 V0 V3 V1 S2 S0 S1 V7 Pin Assignments |
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