ICS525-01/02

OSCaR™ User Configurable Clock

MDS 525-01/02 I

7

Revision 071100

Printed 11/13/00

Integrated Circuit Systems, Inc. • 525 Race Street •San Jose• CA • 95126•(408) 295-9800tel• www.icst.com

Parameter

Conditions

Minimum

Typical

Maximum

Units

AC CHARACTERISTICS (VDD = 3.3 V unless oth

herwise noted)

Input Frequency, crystal input

5

27

MHz

Input Frequency, clock input

0.5

50

MHz

Output Frequency, VDD = 4.5 to 5.5V

0 °C to 70 °C

1

160

ICS525-01, note 1

-40 °C to +85 °C

1

140

MHz

Output Frequency, VDD = 3.0 to 3.6V

0 °C to 70 °C

1

100

ICS525-01, note 1

-40 °C to +85 °C

1

90

MHz

Output Frequency, VDD = 4.5 to 5.5V

ICS525-02, note 1

-40 °C to +85 °C

1.5

250

MHz

Output Frequency, VDD = 3.0 to 3.6V

ICS525-02, note 1

-40 °C to +85 °C

1

200

MHz

Output Clock Rise Time

0.8 to 2.0V

1

ns

Output Clock Fall Time

2.0 to 0.8V

1

ns

Output Clock Duty Cycle, OD = 2, 4, 6, 8, or 10

at VDD/2

45

49 to 51

55

%

Output Clock Duty Cycle, OD = 3, 5, 7, or 9

at VDD/2

40

60

%

Output Clock Duty Cycle, OD = 1 (-02 only)

at VDD/2

35

65

Power Down Time, PD low to clocks stopped

50

ns

Power Up Time, PD high to clocks stable

10

ms

Absolute Clock Period Jitter, ICS525-01, Note 2

Deviation from mean

±140

ps

One Sigma Clock Period Jitter, ICS525-01, Note 2 One Sigma

45

ps

Absolute Clock Period Jitter, ICS525-02, Note 2

Deviation from mean

±85

ps

One Sigma Clock Period Jitter, ICS525-02, Note 2 One Sigma

30

ps

Electrical Specifications (cont.)

Note 1: The phase relationship between input and output can change at power up. For a fixed phase

relationship see the ICS527.

Note 2: For 16 MHz input, 100 MHz output. Use the -02 for lowest jitter.