MDS 552-03 B

2

Revision 052501

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ICS552-03

Pin Assignment

Input Source Select

Pin Descriptions

External Components

A minimum number of external components are required for proper operation. Decoupling capacitors of

0.01

µF should be connected between VDD on pin 2 and GND on pin 7,and between VDD on pin 15 and

GND on pin 10, as close to the device as possible. A 33

Ω series terminating resistor should be used on

each clock output if the trace is longer than 1 inch.

To achieve the low output skews that the ICS552-03 is capable of, careful attention must be paid to board

layout. Essentially, all 8 outputs must have identical terminations, identical loads, and identical trace

geometries. If they do not, the output skew will be degraded. For example, using a 30

Ω series termination

on one output (with 33

Ω on the others) will cause at least 15 ps of skew.

12

1

11

2

10

3

9

OE

4

VDD

5

Q0

6

VDD

7

Q1

8

Q2

P3

P2

P1

Q3

P0

INA

GND

GND

16

15

14

13

INB

SELA

16 Pin 173 Mil (0.65mm) TSSOP

SELA

Input

0INB

1INA

Pin

Number

Pin

Name

Pin

Type

Pin Description

1

OE

Input

Output Enable. Tri-states outputs when low.Internal Pull-up resistor

2

VDD

Power

Connect to +2.5 V, +3.3 V or +5.0 V. Must be the same as pin 15

3

Q0

Output

Clock Output Q0

4

Q1

Output

Clock Output Q1

5

Q2

Output

Clock Output Q2

6

Q3

Output

Clock Output Q3

7

GND

Power

Ground

8

INB

Input

Clock Input B. 5 V tolerant input

9

INA

Input

Clock Input A. 5 V tolerant input

10

GND

Power

Ground

11

P0

Output

Clock Output P0

12

P1

Output

Clock Output P1

13

P2

Output

Clock Output P2

14

P3

Output

Clock Output P3

15

VDD

Power

Connect to +2.5 V, +3.3 V or +5.0 V. Must be the same as pin 2

16

SELA

Input

Selects either INA or INB. Internal pull-up resistor