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ICS552-03 数据表(PDF) 4 Page - Integrated Circuit Systems

部件名 ICS552-03
功能描述  LOW SKEW 1 TO 8 CLOCK BUFFER (4 AT 1X, 4 AT 1/2X)
PDF  6 Pages
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制造商  ICST [Integrated Circuit Systems]
网页  http://www.icst.com
标志 ICST - Integrated Circuit Systems

ICS552-03 数据表(HTML) 4 Page - Integrated Circuit Systems

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LOW SKEW 1 TO 8 CLOCK BUFFER (4 AT 1X, 4 AT 1/2X)
MDS 552-03 B
4
Revision 052501
Int egrat ed C i rcuit Syste ms q 525 R a ce S t r eet, San Jose, CA 95126 q t e l (40 8 ) 295 -9800 q
w w w. icst . c om
ICS552-03
DC Electrical Characteristics (continued)
VDD=3.3V ±5%, Ambient temperature 0 to +70
°C, unless stated otherwise
VDD=5V ±5%, Ambient temperature 0 to +70
°C, unless stated otherwise
Notes: 1. Nominal switching threshold is VDD/2
AC Electrical Characteristics
VDD = 2.5V ±5%, Ambient Temperature 0 to +70
° C, unless stated otherwise
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
3.135
3.465
V
Input High Voltage, INA, INB
VIH
Note 1
VDD/2+0.7
5.5
V
Input Low Voltage, INA, INB
VIL
Note 1
VDD/2-0.7
V
Input High Voltage, OE, SELA
VIH
2VDD
V
Input Low Voltage, OE, SELA
VIL
0.4
V
Output High Voltage
VOH
IOH = -25 mA
2.4
V
Output Low Voltage
VOL
IOL = 25 mA
0.8
V
Operating Supply Current
IDD
No load, 100 MHz
25
mA
Short Circuit Current
IOS
Each output
80
mA
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
4.75
5.25
V
Input High Voltage, INA, INB
VIH
Note 1
VDD/2+1
5.5
V
Input Low Voltage, INA, INB
VIL
Note 1
VDD/2-1
V
Input High Voltage, OE, SELA
VIH
2VDD
V
Input Low Voltage, OE, SELA
VIL
0.4
V
Output High Voltage
VOH
IOH = -45 mA
2.4
V
Output Low Voltage
VOL
IOL = 45 mA
0.8
V
Operating Supply Current
IDD
No load, 100 MHz
45
mA
Short Circuit Current
IOS
Each output
100
mA
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Input Frequency
0
160
MHz
Output Rise Time
tOR
0.8 to 2.0 V, CL=15 pF
1.5
ns
Output Fall Time
tOF
2.0 to 0.8 V, CL=15 pF
1.5
ns
Propagation Delay
Note 1
6.5
ns
Output to output skew. Between
any two Q outputs
Note 2
Rising edges at VDD/2
0
50
ps
Output to output skew. Between
any two P outputs
Note 2
Rising edges at VDD/2
0
50
ps
Output to output skew. Between
any P to any Q output
Note 2
Rising edges at VDD/2
0
100
ps
Input A to Input B skew.
Note 3
0
50
ps



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