ICS552G-02 datasheet(5/6 Pages) ICST

5 / 6 page

LOW SKEW 2 INPUT MUX AND 1 TO 8 CLOCK

MDS 552-02 B

Revision 050401

Int egrat ed C i rcuit Syste ms q 525 R a ce S t r eet, San Jose, CA 95126 q t e l (40 8 ) 295 -9800 q

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PRE L IMINA R Y INF O RMA T IO N

ICS552-02

AC Electrical Characteristics

VDD = 2.5V ±5%, Ambient Temperature 0 to +70

° C, unless stated otherwise

VDD = 3.3V ±5%, Ambient Temperature 0 to +70

° C, unless stated otherwise

VDD = 5.0V ±5%, Ambient Temperature 0 to +70

° C, unless stated otherwise

Notes: 1. With rail-to-rail input clock.

2. Between any two outputs with equal loading.

3. Propagation delay matching through the part.

4. Duty cycle on outputs will match incoming clock duty cycle. Consult ICS for tight duty cycle clock

generators.

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

Input Frequency

200

MHz

Output Rise Time

tOR

0.8 to 2.0 V, CL=15 pF

1.5

Output Fall Time

tOF

2.0 to 0.8 V, CL=15 pF

1.5

Propagation Delay

Note 1

3.5

Output to output skew

Note 2

Rising edges at VDD/2

Input A to Input B skew

Note 3

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

Input Frequency

200

MHz

Output Rise Time

tOR

0.8 to 2.0 V, CL=15 pF

1.0

Output Fall Time

tOF

2.0 to 0.8 V, CL=15 pF

1.0

Propagation Delay

Note 1

3.0

Output to output skew

Note 2

Rising edges at VDD/2

Input A to Input B skew

Note 3

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

Input Frequency

200

MHz

Output Rise Time

tOR

0.8 to 2.0 V, CL=15 pF

0.7

Output Fall Time

tOF

2.0 to 0.8 V, CL=15 pF

0.7

Propagation Delay

Note 1

2.8

Output to output skew

Note 2

Rising edges at VDD/2

Input A to Input B skew

Note 3

ICS552G-02 数据表(PDF) 5 Page - Integrated Circuit Systems

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