ICS571

Low Phase Noise Zero Delay Buffer

MDS 571 B

2

Revision 072899

Printed 11/14/00

Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax

PRELIMINARY INFORMATION

Number

Name

Type

Description

1

ICLK

CI

Reference clock input.

2

VDD

P

Connect to +3.3V or +5V. Must be same as other VDD.

3

GND

P

Connect to ground.

4

CLK/2

O

Clock output per Table above. Low skew divide by two of pin 7 clock.

5

GND

P

Connect to ground.

6

VDD

P

Connect to +3.3V or +5V. Must be same as other VDD.

7

CLK

O

Clock output per Table above.

8

FBIN

CI

Feedback clock input. Connect to CLK or CLK/2 per table above.

Pin Descriptions

Key: CI = clock input, I = input, O = output, P = power supply connection

External Components

The ICS571 requires a 0.01 µF decoupling capacitor to be connected between VDD and GND on each

side of the chip (between pins 2 and 3, and also between pins 6 and 5). They must be connected close to

the ICS571 to minimize lead inductance. No external power supply filtering is required for this device.

A 33

Ω terminating resistor can be used next to each output pin.

Pin Assignment

1

8

2

3

4

7

6

5

ICLK

VDD

GND

CLK/2

FBIN

CLK

VDD

GND

Feedback From

CLK

CLK/2

Input Range

CLK

Input clock frequency

Input clock frequency/2

20 -160 MHz

CLK/2

2xInput clock frequency

Input clock frequency

10 - 80 MHz

Feedback Configuration Table and Frequency Ranges (at 3.3V)