ICS571

Low Phase Noise Zero Delay Buffer

MDS 571 B

1

Revision 072899

Printed 11/14/00

Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax

PRELIMINARY INFORMATION

• Packaged in 8 pin SOIC.

• Can function as low phase noise x2 multiplier.

• Low skew outputs. One is ÷2 of other.

• Input clock frequency up to 160 MHz at 3.3V.

• Phase noise of better than -100 dBc/Hz from

1kHz to 1MHz offset from carrier

• Can recover poor input clock duty cycle.

• Output clock duty cycle of 45/55 at 3.3V.

• High drive strength for >100 MHz outputs.

• Full CMOS clock swings with 25mA drive

capability at TTL levels.

• Advanced, low power CMOS process.

• Operating voltages of 3.0 to 5.5 V.

The ICS571 is a high speed, high output drive, low

phase noise Zero Delay Buffer (ZDB) which

integrates ICS’ proprietary analog/digital Phase

Locked Loop (PLL) techniques. ICS introduced

the world standard for these devices in 1992 with

the debut of the AV9170, and updated that with

the ICS570. The ICS571, part of ICS’

higher frequencies, with faster rise and fall times,

and with lower phase noise. The zero delay feature

means that the rising edge of the input clock aligns

with the rising edges of both outputs, giving the

appearance of no delay through the device. There

are two outputs on the chip, one being a low-skew

divide by two of the other.

The chip is ideal for synchronizing outputs in a

large variety of systems, from personal computers

to data communications to video. By allowing off-

chip feedback paths, the ICS571 can eliminate the

delay through other devices. The use of dividers in

the feedback path will enable the part to multiply

by more than two.

Block Diagram

Description

Features

Phase

Detector,

Charge

Pump, and

Loop Filter

Voltage

Controlled

Oscillator

CLK

Output

Buffer

ICLK

CLK/2

Output

Buffer

FBIN

÷2

External feedback can come from CLK or CLK/2 (see table on page 2).