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ICS620-01RT 数据表(PDF) 3 Page - Integrated Circuit Systems |
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ICS620-01RT 数据表(HTML) 3 Page - Integrated Circuit Systems |
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3 / 4 page ![]() ICS620-01 Digital Still Camera Clock Source MDS 620-01 B 3 Revision 072098 Printed 12/4/00 Integrated Circuit Systems • 1271 Parkmoor Ave.•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax PRELIMINARY INFORMATION I C R O C LOC K Electrical Specifications External Components The ICS620-01 requires some inexpensive external components for proper operation. Decoupling capacitors of 0.1µF should be connected on VDD pins 5, 7+8, and 21 to ground, as close to the ICS620-01 as possible. A series termination resistor of 33 Ω should be used for each clock output. The 14.31818 MHz crystal should be parallel resonant with an accuracy of 30ppm or better. For tuning, the formula 2•(CL-6) gives the value of each capacitor that should be connected between X1 and ground and X2 and ground, where CL = the crystal load (or “correlation”) capacitance. Parameter Conditions Minimum Typical Maximum Units ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD Referenced to GND 7 V Inputs and Clock Outputs Referenced to GND -0.5 VDD+0.5 V Ambient Operating Temperature 0 70 °C Soldering Temperature Max of 10 seconds 260 °C Storage temperature -65 150 °C DC CHARACTERISTICS Operating Voltage, VDD 3 5.5 V Input High Voltage, VIH Pins 6, 16, 20, 24, 27 2 V Input Low Voltage, VIL Pins 6, 16, 20, 24, 27 0.8 V Input High Voltage, VIH Pins 1, 9, 28 VDD-0.5 V Input Mid-level Voltage Pins 1, 9, 28 Leave pin unconnected or tri-stated Leave pin unconnected or tri-stated Leave pin unconnected or tri-stated V Input Low Voltage, VIL Pins 1, 9, 28 0.5 V Output High Voltage, VOH IOH=-4mA VDD-0.4 V Output High Voltage, VOH IOH=-25mA 2.4 V Output Low Voltage, VOL IOL=25mA 0.4 V Operating Supply Current, IDD No Load TBD mA Short Circuit Current Each output ±70 mA On-Chip Pull-up Resistor Pins 6, 16, 20, 24, 27 250 k Ω Input Capacitance All inputs but X1 7 pF AC CHARACTERISTICS Input Frequency 14.31818 MHz Output Clock Rise Time 0.8 to 2.0V TBD ns Output Clock Fall Time 2.0 to 0.8V TBD ns Output Clock Duty Cycle at VDD/2 45 49 to 51 55 % Absolute Jitter TBD ps Note: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability. |
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