The ICS620-01 is a low cost, low jitter, high

performance clock synthesizer for digital still

cameras. Using analog Phase-Locked Loop

(PLL) techniques, the device uses a

14.318 MHz crystal input to produce multiple

output clocks required in the camera. It

provides selectable NTSC/PAL clock, a

selectable processor clock, a selectable CCD

clock, and a selectable interface clocks. Most

clocks are generated to a very low ppm

synthesis error rate.

All clocks can be turned off using a power

down mode. Custom versions with user-

defined frequencies and power down modes

are available in 6-8 weeks.

ICS620-01

Digital Still Camera Clock Source

MDS 620-01 B

1

Revision 072098

Printed 12/4/00

Integrated Circuit Systems • 1271 Parkmoor Ave.•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax

PRELIMINARY INFORMATION

I C R O

Block Diagram

Description

Features

• Packaged in 28 pin, 150 mil wide SSOP (QSOP)

• Provides all clocks necessary for many digital still

camera systems

• All clocks are frequency locked together

• Interface clock for USB, P1394, or UART

• Saves space over multiple crystals and oscillators

• Clocks power down when all select pins are low

• Full CMOS outputs also compatible with TTL levels

• +3.3 V or +5 V operation

• Low power, sub-micron CMOS process

• Custom versions available

Crystal

Oscillator

PLL Clock

Synthesis

Circuitry

CCD Clock 1

Processor Clock 1

2

NSEL1:0

14.31818

MHz

crystal

X1

X2

NTSC/PAL Clock 1

Interface Clock 2

Output

Buffer

PLL Clock

Synthesis

Circuitry

PLL Clock

Synthesis

Circuitry

PLL Clock

Synthesis

Circuitry

PSEL1:0

2

CSEL1:0

2

2

ISEL1:0

Output

Buffer

Output

Buffer

Output

Buffer

Interface Clock 1

CCD Clock 2

÷2

Output

Buffer

Output

Buffer

Output

Buffer

Output

Buffer

NTSC/PAL Clock 2

Processor Clock 2

÷2

÷2