2

ICS9159-20

Pin Descriptions

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

1, 8, 20, 26

VDD

PWR

Power for logic, PCLK and fixed frequency output buffers.

2X1

IN

XTAL or external reference frequency input. This input includes XTAL load

capacitance and feedback bias for a 12 - 16 MHz crystal, nominally 14.31818 MHz.

3

X2

OUT

XTAL output which includes XTAL load capacitance.

4, 11, 17, 23

GND

PWR

Ground for logic, PCLK and fixed frequency output buffers.

5

BSEL

IN

The DISK controller clock is fixed at 33 MHz (with 14.318 MHz input).

6, 7, 9, 10, 24

BOUT(0:4)

OUT

Uncommitted clock buffer outputs.

13, 12

FS(0:1)

IN

Frequency multiplier select pins. See table above. These inputs have internal pull-up

devices. 14 BIN IN Uncommitted buffered inputs.

15, 16, 18, 19,

21, 22, 27

BCLK(0:6)

OUT

Bus clock outputs are fixed at 33.3 MHz or one half the CPU frequency. 25 CPU

OUT Processor clock outputs which are a multiple of the input reference frequency

as shown in the table above.

28

REF

OUT

REF is a buffered copy of the crystal oscillator or reference input clock,

nominally 14.31818 MHz.

Note: BCLK buffers cannot be supplied with 5 volts (Pins 14 and 20) if CPU and fixed frequencies (Pins 1, 8 and 26) are being

supplied with 3.3 volts.