ICS9177 datasheet(2/8 Pages) ICST

2 / 8 page

ICS9177

Pin Description

*Internal pull-up resistor

NUM-

BER

NAME

TYPE

DESCRIPTION

GND

REFCLK

INPUT

from external oscillator

FBCLK

INPUT

external PLL Feedback path

from one of the OutC

outputs

DSEL1#

INPUT

PLL divider mode control

(Contains internal pull-up

resistors)

DSEL0#

INPUT

TESTEN

INPUT

Test mode ENABLE pin

TSTCLK

INPUT

External Test Clk

8NC

9VCC

GND

PCOUT1

OUTPUT TTL - Group 2

Programmable clock outputs

PCOUT0

OUTPUT

GND

VCC

PBOUT1

OUTPUT TTL - Group 1

Programmable clock outputs

PBOUT0

OUTPUT

VCC

GND

PAOUT1

OUTPUT TTL - Group 0

Programmable clock outputs

PAOUT0

OUTPUT

VCC

GND

RESETL

INPUT

Low true divider reset pin

BOUT1

OUTPUT

TTL - 50 MHz output clock

BOUT0

OUTPUT

VCC

GND

NUM-

BER

NAME

TYPE

DESCRIPTION

COUT2

OUTPUT

TTL - 25 MHz output clock

COUT1

OUTPUT

VCC

GND

COUT0

TTL - 25 MHz output clock

DOUT0

TTL - 12.5 MHz output

clock

GND

AOUT1

OUTPUT ECL - 100 MHz, 75 MHz or

50 MHz based on DSEL(1:0)

pins

AOUT0

OUTPUT

GND

ECL+5V

(same as

VCC)

ANALO-

G +5V

ANALO-

G +5V

AGND

PCSEL1

INPUT

Programmable clock Group

C select

PCSEL0

INPUT

PBSEL1

INPUT

Programmable clock Group

B select

PBSEL0

INPUT

PASEL1

INPUT

Programmable clock Group

A select

PASEL0

INPUT

ICS9177 数据表(PDF) 2 Page - Integrated Circuit Systems

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ICS9177 数据表(PDF) 2 Page - Integrated Circuit Systems

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