6

ICS9177

Table 6: AC Specification type Out B.ttl Pins

(50 MHz)

Test Load Conditions: 500

Ω, 15 pF.

Note 1: Pin skew is measured from the earliest rising edge of the group to the latest rising edge of the group.

Note 2: Delay is the intrinsic delay between the TTL drivers switching and the PECL driver switching. This is measured from

the OutA.pecl signal at the signal swing mid-point to max output of the OutB.ttl signal’s rising edge

Table 7: AC Specification type Out C.ttl Pins

(25 MHz)

Test Load Conditions: 500

Ω, 15 pF.

Note 1: Pin skew is measured from the earliest rising edge of the group to the latest rising edge of the group.

Note 2: Spread is the absolute difference between the rising edge of any OutC.ttl signal and the rising edge of any OutB.ttl

signal

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Output High Voltage

Voh

2.4

3.2

5

volts

Output Low Voltage

Vol

0

0.3

0.8

volts

Output High Current

Ioh

16

mA

Output Low Current

Iol

24

mA

Rise Time 10-90%

tr

1

2

3

ns

Fall Time 10-90%

tf

1

2

3

ns

Pin skew to other OutB.ttl

tsk

250

500

ps

Duty cycle at 1.5V

dcyc

45

55

%

Delay from OutA.pecl signals

2

tdly

.2

.5

ns

Skew associated with above

delay

3

tdlyskw

±0.5

ns

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

UNITS

Output High Voltage

Voh

2.4

3.2

5

volts

Output Low Voltage

Vol

0

0.3

0.8

volts

Output High Current

Ioh

16

mA

Output Low Current

Iol

24

mA

Rise Time 10-90%

tr

1

2

3

ns

Fall Time 10-90%

tf

1

2

3

ns

Pin skew to other OutC.ttl

signals

1

tsk

250

500

ps

Duty cycle at 1.5V

dcyc

45

55

%

Spread to OutB.ttl signals

2

tspb

500

ps