数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

80296SA 数据表(PDF) 16 Page - Intel Corporation

部件名 80296SA
功能描述  80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
PDF  40 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  INTEL [Intel Corporation]
网页  http://www.intel.com
标志 INTEL - Intel Corporation

80296SA 数据表(HTML) 16 Page - Intel Corporation

Back Button 80296SA Datasheet HTML 12Page - Intel Corporation 80296SA Datasheet HTML 13Page - Intel Corporation 80296SA Datasheet HTML 14Page - Intel Corporation 80296SA Datasheet HTML 15Page - Intel Corporation 80296SA Datasheet HTML 16Page - Intel Corporation 80296SA Datasheet HTML 17Page - Intel Corporation 80296SA Datasheet HTML 18Page - Intel Corporation 80296SA Datasheet HTML 19Page - Intel Corporation 80296SA Datasheet HTML 20Page - Intel Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 16 / 40 page
background image
12
PRELIMINARY
80296SA COMMERCIAL CHMOS 16-BIT MICROCONTROLLER
TXD
O
Transmit Serial Data
In serial I/O modes 1, 2, and 3, TXD transmits serial port output data. In mode 0, it is
the serial clock output.
TXD shares a package pin with P2.0.
V
CC
PWR
Digital Supply Voltage
Connect each V
CC pin to the digital supply voltage.
V
SS
GND
Digital Circuit Ground
These pins supply ground for the digital circuitry. Connect each V
SS pin to ground
through the lowest possible impedance path.
WR#
O
Write
This active-low output indicates that an external write is occurring. This signal is
asserted only during external memory writes.
WR# shares a package pin with WRL#.
Chip configuration register 0 (CCR0) determines whether this pin functions as
WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.
WRH#
O
Write High
During 16-bit bus cycles, this active-low output signal is asserted for high-byte writes
and word writes to external memory. During 8-bit bus cycles, WRH# is asserted for
all write operations.
WRH# shares a package pin with BHE#.
Chip configuration registrer 0 (CCR0) determines whether this pin functions as
BHE# or WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects WRH#.
WRL#
O
Write Low
During 16-bit bus cycles, this active-low output signal is asserted for low-byte writes
and word writes to external memory. During 8-bit bus cycles, WRL# is asserted for
all write operations.
WRL# shares a package pin with WR#.
Chip configuration register 0 (CCR0) determines whether this pin functions as
WR# or WRL#. CCR0.2 = 1 selects WR#; CCR0.2 = 0 selects WRL#.
XTAL1
I
Input Crystal/Resonator or External Clock Input
Input to the on-chip oscillator, internal phase-locked loop circuitry, and the internal
clock generators. The internal clock generators provide the peripheral clocks, CPU
clock, and CLKOUT signal. When using an external clock source instead of the on-
chip oscillator, connect the clock input to XTAL1. The external clock signal must
meet the V
IH specification for XTAL1.
XTAL2
O
Inverted Output for the Crystal/Resonator
Output of the on-chip oscillator inverter. Leave XTAL2 floating when the design uses
an external clock source instead of the on-chip oscillator.
Table 4. Signal Descriptions (Continued)
Name
Type
Description



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com