82527

AC Characteristics for 8-Bit Non-Multiplexed Asynchronous (Mode 3)

Symbol

Parameter

Min

Max

8 MHz

16 MHz

4 MHz

10 MHz

2 MHz

8 MHz

Address or RW

Valid to CS

Low

3 ns

Setup

CS

Low to Data Valid

0 ns

55 ns

for High Speed Registers (02H 04H 05H)

For Low Speed Registers

0 ns

For Low Speed Registers

0 ns

DSACK0

Low to Output Data Valid

23 ns

for High Speed Read Register

For Low Speed Read Register

k

0ns

82527 Input Data Hold after CS

High

15 ns

82527 Output Data Hold after CS

High

0 ns

CS

High to Output Data Float

35 ns

CS

High to DSACK0

e

0ns

55ns

CS

High to DSACK0

e

28V

150 ns

CS

High to DSACK0

Float

0 ns

100 ns

CS

Width between Successive Cycles

25 ns

CS

High to Address Invalid

7 ns

CS

High to RW

Invalid

5 ns

CS

Width Low

65 ns

CPU Write Data Valid to CS

High

20 ns

CS

Low to DSACK0

Low

0ns

67ns

for High Speed Registers and Low Speed

Registers Write Access without Previous

End of Previous Write (CS

High) to

0 ns

DSACK0

Low for a Write Cycle with a

CLKOUT Period

CLKOUT High Period

NOTES

E and AS must be tied high in this mode

1 Definition of ‘‘Read Cycle without a Previous Write’’ The time between the rising edge of CS

(for the previous write

cycle) and the falling edge of CS

2 Definition of ‘‘Write Cycle without a Previous Write’’ The time between the rising edge of CS

(for the previous write

cycle) and the rising edge of CS

3 An on-chip pullup will drive DSACK0

to approximately 24V An external pullup is required to drive this signal to a higher

voltage

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