AUTOMOTIVE 8XC196KB

PIN DESCRIPTIONS

Symbol

Name and Function

Main Supply Voltage (a5V)

of the AD converter and the logic used to read Port 0 Must be connected for AD and Port 0

to function

ANGND

Reference Ground for the AD Converter Must be held at nominally the same potential as

Programming Voltage for the EPROM Parts It should be a1275V for programming This pin

XTAL1

Input of the Oscillator Inverter and the Internal Clock Generator

XTAL2

Output of the Oscillator Inverter

CLKOUT

Output of the Internal Clock Generator The frequency of CLKOUT is

the oscillator

frequency It has a 50% duty cycle

RESET

Reset Input to the Chip Input low for at least 4 state times will reset the chip The subsequent

low to high transition resynchronizes CLKOUT and commences a 10-state time sequence in

which the PSW is cleared a byte is read from 2018H loading the CCB and a jump to location

2080H is executed Input high for normal operation RESET has an internal pullup

BUSWIDTH

Input for Bus Width Selection If CCR bit 1 is a one this pin selects the buswidth for the bus

cycle in progress If BUSWIDTH is low an 8-bit cycle occurs If BUSWIDTH is high a 16-bit

cycle occurs If CCR bit 1 is a 0 the bus is always an 8-bit bus This pin is the TEST pin on the

NMI

A positive transition causes an interrupt vector through external memory location 203EH

INST

Output High during an External Memory Read Indicates the read is an instruction fetch INST

is valid throughout the bus cycle INST is active only during external memory fetches during

internal EPROMROM fetches INST is held low

EA

Input for Memory Select (External Access) EA equal to a TTL-high causes memory accesses

to locations 2000H through 3FFFH to be directed to on-chip EPROMROM EA equal to a

TTL-low causes accesses to these locations to be directed to off-chip memory EA e

a

1275V causes execution to begin in the Programming Mode EA has an internal pulldown

so it defaults to execute from external memory unless otherwise driven EA is latched at

reset

ALEADV

Address Latch Enable or Address Valid Output as Selected by CCR Both pin options provide

a latch to demultiplex the address from the addressdata bus When the pin is ADV it goes

inactive (high) at the end of the bus cycle ADV can be used as a chip select for external

memory ALEADV is active only during external memory accesses

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