AUTOMOTIVE 8XC196KB

Symbol

Name and Function

RD

Read Signal Output to External Memory RD is active only during external memory reads

WR WRL

Write and Write Low Output to External Memory as Selected by the CCR WR will go low

for every external write while WRL will go low only for external writes where an even byte is

being written WR WRL is active during external memory writes

BHE WRH

Byte High Enable or Write High Output as Selected by the CCR BHE e 0 selects the bank

of memory that is connected to the high byte of the data bus A0 e 0 selects that bank of

memory that is connected to the low byte Thus accesses to a 16-bit wide memory can be

to the low byte only (A0 e 0 BHE e 1) to the high byte only (A0 e 1 BHE e 0) or both

bytes (A0 e 0 BHE e 0) If the WRH function is selected the pin will go low if the bus

cycle is writing to an odd memory location BHE WRH is only valid during 16-bit external

memory write cycles

READY

Ready Input to lengthen external memory cycles for interfacing with slow or dynamic

memory or for bus sharing If the pin is high CPU operation continues in a normal manner

If the pin is low prior to the falling edge of CLKOUT the memory controller goes into a wait

state mode until the next positive transition in CLKOUT occurs with READY high When

external memory is not used READY has no effect The number of wait states inserted into

the bus cycle is controlled by the CCR

HSI

Inputs to High Speed Input Unit Four HSI pins are available HSI0 HSI1 HSI2 HSI3

Two of which are shared with the HSO Unit (HSI2 and HSI3) The HSI pins are also used

as the SID in Slave Programming Mode

HSO

Outputs from High Speed Output Unit Six HSO pins are available (HSO0 through HSO5)

HSO4 and HSO5 are shared with HSI

PORT 0

8-Bit High Impedance Input-Only Port These pins can be used as digital inputs andor as

analog inputs to the on-chip AD converter These pins are also used as inputs to EPROM

parts to select the Programming Mode

PORT 1

8-Bit Quasi-Bidirectional IO Port

PORT 2

8-Bit Multi-Functional Port All of its pins are shared with other functions

PORT 3 and 4

8-Bit Bidirectional IO Ports with Open Drain Outputs These pins are shared with the

multiplexed addressdata bus which has strong internal pullups

HOLD

Bus Hold Input Requesting Control of the Bus Enabled by Setting WSR7

HLDA

Bus Hold Acknowledge Output Indicating Release of the Bus Enabled by setting WSR7

BREQ

Bus Request Output Activated when the bus controller has a pending external memory

cycle Enabled by setting WSR7

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